700 Mbps/pin CMOS signalling interface using current integrating receivers

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1996, Pages 142-143

  Sidiropoulos, Stefanos ^a   Horowitz, Mark ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; DIGITAL CIRCUITS; ELECTRIC CURRENTS; ELECTRIC DELAY LINES; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT MANUFACTURE; INTERCONNECTION NETWORKS; INTERFACES (COMPUTER); MULTIPROCESSING SYSTEMS; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE;

CMOS DIGITAL CHIPS; CMOS SIGNALLING INTERFACE; CURRENT INTEGRATING RECEIVERS;

SIGNAL RECEIVERS;

EID: 0029707022     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)