The Design of Reliable Devices for Mission-Critical Applications

IEEE Transactions on Instrumentation and Measurement

Volumn 52, Issue 6, 2003, Pages 1703-1712

  Bolchini, Cristiana ^a   Pomante, Luigi ^b   Salice, Fabio ^a   Sciuto, Donatella ^a  

^a POLITECNICO DI MILANO   (Italy)

^b CEFRIEL   (Italy)

Author keywords

Digital design of reliable systems; Fault observability; Hardware faults; Totally self checking (TSC); TSC quality

Indexed keywords

FAILURE ANALYSIS; FUNCTIONS; PROBABILITY; SIGNALING; VECTORS;

DIGITAL DESIGN; FAULT OBSERVABILITY; HARDWARE FAULTS; TOTALLY SELF-CHECKING (TSC);

DIGITAL DEVICES;

EID: 0344013030     PISSN: 00189456     EISSN: None     Source Type: Journal    
DOI: 10.1109/TIM.2003.818736     Document Type: Article

References (15)

1. J. E. Smith and G. Metze, "Strongly fault secure logic networks," IEEE Trans. Computer, vol. C-27, pp. 491-499, June 1978.
2. K. De, C. Natarajan, D. Nair, and P. Banerjee, "RSYN: A system for automated synthesis of reliable multi-level circuits," IEEE Trans. VLSI Syst., vol. 2, pp. 186-195, June 1994.
3. D. K. Pradhan, Ed., Fault-Tolerant Computing, Theory and Techniques. Englewood Cliffs, NJ: Prentice-Hall, 1986, vol. 1.
4. S. Mitra and E. J. McCluskey, "Diversity techniques for concurrent error detection," in Proc. Int. Symp. Quality Electronic Design, 2001, pp. 249-250.
5. M. Favalli and C. Metra, "On the design of self-checking functional units based on Shannon circuits," in Proc. Design, Automation and Test in Europe Conf. Exhibition 1999, 1999, pp. 368-375.
6. J. C. Lo and E. Fujiwara, "Probability to achieve TSC goal," IEEE Trans. Computer, vol. 45, pp. 450-460, Apr. 1996.
7. _, "A probabilistic measurement for Totally Self-Checking circuits," Proc. Int. Workshop on Defect and Fault Tolerance in VLSI Systems, pp. 263-270, 1993.
8. R. K. Brayton, R. Rudell, and A. Sangiovanni-Vincentelli, "Multilevel logic synthesis," Proc. IEEE, vol. 78, no. 2, pp. 264-300, Feb. 1990.
9. N. A. Touba and E. J. McCluskey, "Logic synthesis techniques for reduced area implementation of multilevel circuits with concurrent error detection," in Proc. Int. Conf. Computer-Aided Design (ICCAD), 1994, pp. 651-654.
10. V. V. Saposhnikov, A. Morosov, VI. V. Saposhnikov, and M. Gössel, "Design of self-checking combinational circuits with low area overhead," J. Electron. Testing Theory Applicat. (JETTA), vol. 12, no. 1/2, pp. 41-54, Feb.-Apr. 1998.
11. C. Bolchini, F. Salice, and D. Sciuto, "Conditions for design of circuits with concurrent error detection properties," in Proc. ISCAS, Hong Kong, 1997, pp. 2741-2744.
12. _, "Fault analysis for networks with concurrent error detection," IEEE Des. Test Comput., pp. 66-74, Oct.-Dec. 1998.
13. _, "A scalar cost function for analyzing the quality of Totally Self-Checking design methodologies," in Proc. Int. Conf. Innovative Systems in Silicon (ISIS), Austin, TX, 1997, pp. 196-200b.
14. E. M. Sentovich, K. J. Singh, C. Moon, H. Savoj, R. K. Brayton, and A. Sangiovanni-Vincentelli, "Sequential circuit design using synthesis and optimization," in Proc. IEEE Int. Conf. Computer Design: VLSI in Computers and Processors (ICCD), 1992, pp. 328-333.
15. A. P. Kakarountas, K. S. Papadomanolakis, S. Nikolaidis, D. Soudris, and C. Goutis, "Confronting violations of the TSCG(T) in low-power design," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 4, 2002, pp. IV-313-IV-316.