메뉴 건너뛰기




Volumn 36, Issue 4, 2003, Pages 175-189

Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications

Author keywords

Analog integrated circuits; Low voltage low power design; Operational amplifiers; Pipelined A D converters

Indexed keywords

ELECTRIC CONVERTERS; ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEMS; MOS CAPACITORS; OPERATIONAL AMPLIFIERS; SIGNAL TO NOISE RATIO; SWITCHING NETWORKS;

EID: 0344012020     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2003.08.001     Document Type: Article
Times cited : (22)

References (12)
  • 1
    • 0020906580 scopus 로고
    • An improved frequency compensation technique for CMOS operational amplifiers
    • Ahuja B.K. An improved frequency compensation technique for CMOS operational amplifiers. IEEE J. Solid-State Circuits. SC-18:1983;629-633.
    • (1983) IEEE J. Solid-state Circuits , vol.SC-18 , pp. 629-633
    • Ahuja, B.K.1
  • 2
    • 0036296625 scopus 로고    scopus 로고
    • A low-voltage low-power fast-settling operational amplifier for use in high-speed high-resolution pipelined A/D converters
    • May
    • R. Lotfi, O. Shoaei, A low-voltage low-power fast-settling operational amplifier for use in high-speed high-resolution pipelined A/D converters, in: Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 2002, Vol. II, May 2002, pp. 416-419.
    • (2002) Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 2002 , vol.2 , pp. 416-419
    • Lotfi, R.1    Shoaei, O.2
  • 3
    • 0021622790 scopus 로고
    • Design techniques for cascaded CMOS opamps with improved PSRR and common-mode input range
    • Ribner D.B., Copeland M.A. Design techniques for cascaded CMOS opamps with improved PSRR and common-mode input range. IEEE J. Solid-State Circuits. SC-19:1984;919-925.
    • (1984) IEEE J. Solid-state Circuits , vol.SC-19 , pp. 919-925
    • Ribner, D.B.1    Copeland, M.A.2
  • 7
    • 0031169153 scopus 로고    scopus 로고
    • A 1.8-V digital-audio sigma-delta modulator in 0.8- μm CMOS
    • Rabii S., Wooley B. A 1.8-V digital-audio sigma-delta modulator in 0.8-. μm CMOS IEEE J. Solid-State Circuits. 32:1997;783-796.
    • (1997) IEEE J. Solid-state Circuits , vol.32 , pp. 783-796
    • Rabii, S.1    Wooley, B.2
  • 8
    • 0033881636 scopus 로고    scopus 로고
    • Low-voltage dynamic biasing technique for CMOS class-AB current mode circuits
    • Palmisano G., Pennisi S. Low-voltage dynamic biasing technique for CMOS class-AB current mode circuits. IEE Electron. Lett. 36(2):2000;114-115.
    • (2000) IEE Electron. Lett. , vol.36 , Issue.2 , pp. 114-115
    • Palmisano, G.1    Pennisi, S.2
  • 10
    • 0034461867 scopus 로고    scopus 로고
    • Dynamic biasing for true low-voltage CMOS class-AB current-mode Circuits
    • Palmisano G., Pennisi S. Dynamic biasing for true low-voltage CMOS class-AB current-mode Circuits. IEEE Trans. Circuits Systems. 47(12):2000;1569-1575.
    • (2000) IEEE Trans. Circuits Systems , vol.47 , Issue.12 , pp. 1569-1575
    • Palmisano, G.1    Pennisi, S.2
  • 12
    • 0032664038 scopus 로고    scopus 로고
    • A 1.5-V 10-bit, 14.3MS/s CMOS pipeline analog-to-digital converter
    • Abo A.M., Gray P.R. A 1.5-V 10-bit, 14.3MS/s CMOS pipeline analog-to-digital converter. IEEE J. Solid-State Circuits. 34:1999;599-606.
    • (1999) IEEE J. Solid-state Circuits , vol.34 , pp. 599-606
    • Abo, A.M.1    Gray, P.R.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.