A low-voltage low-power fast-settling operational amplifier for use in high-speed high-resolution pipelined A/D converters

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2002, Pages

  Lotfi, Reza ^a   Shoaei, Omid ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC LOADS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POTENTIAL; GAIN MEASUREMENT;

CASCODE COMPENSATION; MILLER COMPENSATION; SLEW RATE PERFORMANCE;

OPERATIONAL AMPLIFIERS;

EID: 0036296625     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Design for reliability of low-voltage, switched-capacitor circuits
2. A 1.5-V 10-bit, 14.3MS/s CMOS pipeline analog-to-digital converter
3. 1-V 9-bit pipelined switched-opamp ADC
4. Systematic design for optimization of high-speed self-calibrated pipelined A/D converters
5. An improved frequency compensation technique for CMOS operational amplifiers
6. Design techniques for cascoded CMOS opamps with improved PSRR and common-mode input range
7. High-speed, low-power sigma-delta modulators for RF base-band channel applications
8. A 1.8-V digital-audio sigma-delta modulator in 0.8-μm CMOS
9. A 10 bit 20Msamples/s, 35 mW pipeline A/D converter
10. A fast-settling CMOS opamp for SC circuits with 90-dB DC gain