A 1.1 W single-chip MPEG-2 HDTV CODEC LSI for embedding in consumer-oriented mobile CODEC systems

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 177-180

  Iwasaki, Hiroe ^a   Naganuma, Jiro ^a   Nakajima, Yasuyuki ^a   Tashiro, Yutaka ^a   Nakamura, Ken ^a   Yoshitome, Takeshi ^a   Onishi, Takayuki ^a   Ikeda, Mitsuo ^a   Izuoka, Takaaki ^a   Endo, Makoto ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; EMBEDDED SYSTEMS; HIGH DEFINITION TELEVISION; INTEGRATING CIRCUITS; MICROPROCESSOR CHIPS; MULTIPLEXING EQUIPMENT; REDUCED INSTRUCTION SET COMPUTING;

HIGH DEFINITION TELEVISION CODEC; MOBILE CODEC SYSTEMS;

LSI CIRCUITS;

EID: 0242696143     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. ISO/IEC 13818-1/2/3 International Standard, Information Technology - Genetic Coding of Moving Pictures and Associated Audio: Systems/Vidual/Audio -, November 1994.
2. M. Mizuno, Y. Ooi, N. Hayashi, J. Goto, M. Hozumi, K. Furuta, A. Shibayama, Y. Nakazawa, O. Ohnishi, S. Y. Zhu, Y. Yokoyama, Y. Katayama, H. Takano, N. Miki, Y. Senda, and M. Yamashina, "A 1.5-W single-chip MPEG-2 MP@ML video encoder with low power motion estimation and clocking," IEEE Solid-State Circuits, vol. 32, pp. 1807-1816, November 1997.
3. 2 0.95w singlechip MPEG2 MP@ML video encoder with a 128GOPS motion estimator and a multi-tasking RISC-type controller," in International Solid-State Circuits Conference, 1998, pp. 30-31.
4. E. Ogura, M. Takashima, D. Hiranaka, T. Ishikawa, Y. Yanagita, S. Suzuki, T. Fukuda, and T. Ishii, "A 1.2w single-chip MPEG2 video encoder LSI including wide search range motion estimation and 81MOPS controller," in International Solid-State Circuits Conference, 1998, pp. 32-33.
5. S. Ishiwata, T. Yamakage, Y. Tsuboi, T. Shimazawa, T. Kitazawa, S. Machinaka, K. Yahagi, H. Takeda, A. Oue, T. Kodama, N. Matsumoto, T. Kamei, T. Miyamori, G. Ootomo, and M. Matsui, "A Single-Chip MPEG-2 Codec Based on Customized Media Microprocessor," in IEEE 2002 Custom Integrated Circuits Conference, 2002, pp. 163-166.
6. 2 0.7-W Single-Chip MPEG-2 422P@ML Video, Audio, and System Encoder With a 64-Mb Embedded DRAM for Portable 422P@HL Encoder System," in IEEE Journal of Solid-State Circuits, 2002, pp. 450-454.
7. M. Ikeda, T. Kondo, K. Nitta, K. Suguri, T. Yoshitome, T. Minami, J. Naganuma, and T. Ogura, "An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture," in Design, Automation and Test in Europe Conference 1999, March 1999, pp. 44-50.
8. LSI Logic Corporation., "DoMiNo: (2002) LSI Logic home page.," [Online]. Available:http://www.lsilogic.com.
9. H. Iwasaki, J. Naganuma, K. Nitta, K. Nakamura, T. Yoshitome, M. Ogura, Y. Nakajima, Y. Tashiro, T. Onishi, M. Ikeda, and M. Endo, "Single-chip MPEG-2 422P@HL CODEC LSI with Multi-chip Configuration for Large Scale Processing beyond HDTV Level," in Design, Automation and Test in Europe Conference 2003 Designers' Forum, March 2003, pp. 2-7.