An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 44-50

  Ikeda, Mitsuo ^a   Kondo, Toshio ^a   Nitta, Koyo ^a   Suguri, Kazuhito ^a   Yoshitome, Takeshi ^a   Minami, Toshihiro ^a   Naganuma, Jiro ^a   Ohura, Takeshi ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE-BASED; CMOS PROCESSS; COOPERATIVE ARCHITECTURES; DVD-RECORDER; LOW-POWER CONSUMPTION; MPEG-2 VIDEO; SINGLE-CHIP; VIDEO QUALITY;

CMOS INTEGRATED CIRCUITS; EXHIBITIONS; MOTION PICTURE EXPERTS GROUP STANDARDS; SCALABILITY;

HIGH DEFINITION TELEVISION;

EID: 4344673441     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761095     Document Type: Conference Paper

References (10)

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7. E. Miyagoshi et al., "A 100mm2 0.95W Single-Chip MPEG2 MP@ML Video Encoder,..," Proc. of the In-ternational Solid-State Circuits Conference, pp. 30-31, February 1998.
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9. T. Minami et al. "A Single-chip MPEG2 MP@ML Video Encoder LSI with Multi-chip Configuration for a Single-board MP@HL Encoder," Symposium HOT Chips X, August 1998.
10. K. Ochiai et al. "High-speed Software-based Plat-form for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalability," Proc. of the Design, Automation and Test in Europe (DATE99), March 1999.