100 mm2 0.95 W single-chip MPEG2 MP ML video encoder with a 128 GOPS motion estimator and a multi-tasking RISC-type controller

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 1998, Pages 30-31,-409

  Miyagoshi, Eiji ^a   Araki, Toshiyuki ^a   Sayama, Takuya ^a   Ohtani, Akihiko ^a   Minemaru, Takayuki ^a   Okamoto, Kiyoshi ^a   Kodama, Hisashi ^a   Morishige, Takayuki ^a   Watabe, Akihiro ^a   Aoki, Katsuji ^a   Mitsumori, Toshimasa ^a   Imanishi, Hiroshi ^a   Jinbo, Takuya ^a   Tanaka, Yasushi ^a   Taniyama, Masayuki ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; IMAGE CODING; PACKET NETWORKS; PHASE LOCKED LOOPS; RANDOM ACCESS STORAGE; REDUCED INSTRUCTION SET COMPUTING; STATISTICAL METHODS; TELEVISION STANDARDS;

MOTION ESTIMATION; MOTION PICTURE EXPERTS GROUP (MPEG) STANDARDS;

VIDEO SIGNAL PROCESSING;

EID: 0031656308     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)