A full adder implementation using SET based linear threshold gates

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2002, Pages 665-668

  Lageweg, Casper ^a   Cotofana, Sorin ^a   Vassiliadis, Stamatis ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE BUFFERS; CIRCUIT PARAMETER; FEEDBACK EFFECTS; FULL ADDERS; SIMULATION RESULT; SINGLE-ELECTRON TUNNELING; THRESHOLD GATES;

ELECTRON TUNNELING; LOGIC DESIGN; THRESHOLD LOGIC; TRANSIENTS; TUNNEL JUNCTIONS;

ADDERS;

EID: 0242507033     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2002.1046256     Document Type: Conference Paper

References (10)

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