Achieving fanout capabilities in single electron encoded logic networks

2001 6th International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2001 - Proceedings

Volumn 2, Issue , 2001, Pages 1383-1386

  Lageweg, C ^a   Cotofana, S ^a   Vassiliadis, S ^a  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84964459871     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSICT.2001.982159     Document Type: Conference Paper

References (5)

1. A.N.Korotkov. Single-Electron Logic and Memory Devices. International Journal of Electronics, Vol. 86(No. 5):pp. 511-547, 1999.
2. C.Lageweg and S.Cotofana and S.Vassiliadis. A Linear Threshold Gate Implementation in Single Electron Technology. In IEEE Computer Society Workshop on VLSI, pages pp. 93-98, April 2001.
3. C.Wasshuber and H.Kosina. A Single-Electron Device and Circuit Simulator. Superlattices and Microstructures, Vol. 21(No. 1):pp. 37-42, January 1997.
4. K.K.Likharev. Single-Electron Devices and Their Applications. Proceeding of the IEEE, Vol. 87(No. 4):pp. 606-632, April 1999
5. S.Muroga. Threshold Logic and its Applications. Wiley and Sons Inc., 1971.