Study and improvement of electrical performance of 130 nm Cu/CVD low k SiOCH interconnect related to via etch process

Microelectronics Journal

Volumn 34, Issue 11, 2003, Pages 1051-1058

  Tsang, C F ^a   Bliznetsov, V N ^a   Su, Y J ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

Back end of line process integration; Copper interconnects; Failure analysis; Low k dielectrics; Yield improvement

Indexed keywords

COPPER INTERCONNECTS;

CHEMICAL VAPOR DEPOSITION; ETCHING; FAILURE ANALYSIS; RELIABILITY;

DIELECTRIC MATERIALS;

EID: 0142247223     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2003.09.005     Document Type: Article

References (20)

1. Singer P. Copper goes mainstream: low k to follow. Semiconductor International. 20:(13):1997;67-68. See also page 70.
2. Rose K., Mangaser R. Copper interconnect technology - new paradigms for BEOL manufacturing. Proceedings of the IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. 1998;347-353.
3. Chang C.S., Monnig K.A., Melliar-Smith M. Interconnection challenges and the national technology roadmap for semiconductors. Proceedings of the IEEE International Interconnect Technology Conference. 1998;3-6.
4. Naik M., Parikh S., Li P., Educato J., Cheung D., Hashim I., Hey P., Jenq S., Pan T., Redeker F., Rana V., Tang B., Yost D. Process integration of double level copper-low k (k=2.8) interconnect. Proceedings of the IEEE International Interconnect Technology Conference. 1999;181-183.
5. Chang W., Chen C.C., Lu J.C., Liou S.J., Tsai W.J., Liu S.Y., Lee H.J., Wang Y.I., Lin H.C., Yeh C.H., Linliu K., Chang S.Z., Shen S.J., Chen L.W., Peng S.S., Hung S.H., Hsiao Y.L., Hsieh C.N., Li C.I., Chang M., Lee K.H. 300 mm process integration for 0.13 μm generation with Cu/low- k interconnect technology, Technical Digest. International Electron Devices Meeting. 2001;603-606.
6. Fayolle M., Torres J., Passemard G., Fusalba F., Fanget G., Louis D., Assous M., Louveau O., Rivoire M., Haxaire K., Mourier M., Maitrejean S., Besson P., Broussous L., Arnaud L., Feldis H. Integration of Cu/SiOC in Cu dual damascene interconnect for 0.1-μm technology. Microelectronic Engineering. 64:2002;35-42.
7. Ho P.K.K., Zhou M.-S., Gupta S., Chockalingam R., Li J.-X., Fan M.-H. Challenges of damascene etching for copper interconnect. Proceedings of SPIE - the International Society for Optical Engineering. 3883:1999;34-41.
8. Roy M.M., Bliznetsov V.N., Samudra G. A dual BARC method for lithography and etch for dual damascene with low K . Japanese Journal of Applied Physics. 42:2003;2649-2653.
9. Bliznetsov V.N., Badam R.M., Rakesh K., Lan P. Reactive ion etching of vias in low- k OSG films for dual-damascene technology. Proceedings of International Semiconductor Technology Conference. 2002;S512-S518.
10. Li A., Tietz J., Zhu H., Helmer B., Pirkle D., Annapragada R., Chien T., Sadjadi R. New challenges in plasma etching for low-k dual damascene. Yang M. Proceedings of the 1st Electrochemical Society International Semiconductor Technology Conference. 2001;531-538.
11. Zhang Z., Huang J.-S., Twiford M., Martin E., Layadi N., Salah A., Bhowmik B., Vitkavage D., Lytle S., Yeh E.C.C., Tu K.-N. A robust multilevel interconnect module for subquartermicrometer complementary metal oxide semiconductor technology integration. Journal of the Electrochemical Society. 149:(5):2002;G324-G329.
12. Krishnamoorthy A., Bliznetsov V., Tay H.L., Yu B. Effect of etching process deviations and photoresist stripping on contact yield of copper dual damascene metallization. Journal of the Electrochemical Society. 149:(12):2002;G656-G660.
13. Shohji R. High reliability interconnect technology with tungsten-barrier metal in next generation. Proceedings of the 9th International Symposium on Semiconductor Manufacturing. 2000;165-168.
14. Smith B., Blackley S., Carter R., Chheda S., Crabtree P., Farber D., Gall M., Islam R., Jawarani D., King C., Menke D., Nelson R., Pressley L., Smith D., Sparks T., Stephens T., Travis E., Venkatesan S. A comparison of via overetch variations between conventional Al-W and dual-inlaid copper integrations. Proceedings of the IEEE International Interconnect Technology Conference. 1999;106-108.
15. Zheng Y.S., Guo Q., Su Y.J., Foo P.D. Polymer residue chemical composition analysis and its effect on via contact resistance in dual damascene copper interconnects process integration. Microelectronics Journal. 34:2003;109-113.
16. Flinn P.A. Mechanical stress in VLSI interconnections: origins, effects, measurement, and modeling. MRS Bulletin-Materials Research Society. 11:1995;70-73.
17. Ogawa E.T., McPherson J.W., Rosal J.A., Dickerson K.J., Chiu T.-C., Tsung L.Y., Jain M.K., Bonifield T.D., Ondrusek J.C., McKee W.R. Stress-induced voiding under vias connected to wide Cu metal leads. Proceedings of the IEEE International Reliability Physics Symposium. 2002;312-321.
18. von Glasow A., Fischer A.H. New Approaches for the Assessment of Stress-Induced Voiding in Cu Interconnects. Proceedings of the IEEE International Interconnect Technology Conference. 2000;274-276.
19. Lai J.B., Yang J.L., Wang Y.P., Chang S.H., Hwang R.L., Huang Y.S., Hou C.S. A Study of Bimodal Distribution of Time-to-Failure of Copper Via Electromigration. Proceedings of the International Symposium on VLSI Technology, Systems, and Applications. 2001;271-274.
20. Kim D.H., Park J.S., Kim B.C., Lee S.C., Bae M.K., Nam J.W., Park I.S., Kim H.Y., Kim T.K., Choi D.W., Lee J.Y., Kim J.S., Park Y.J., Hong J.I., Park J.W. Analysis of via-void generation mechanism for giga-bit-scale DRAM. Proceedings of the IEEE International Reliability Physics Symposium. 2001;294-298.