Analysis of via-void generation mechanism for giga-bit-scale DRAM

IEEE International Reliability Physics Symposium Proceedings

Volumn 2001-January, Issue , 2001, Pages 294-298

  Kim, D H ^a   Park, J S ^a   Kim, B C ^a   Lee, S C ^a   Bae, M K ^a   Nam, J W ^a   Park, I S ^a   Kim, H Y ^a   Kim, T K ^a   Choi, D W ^a   Lee, J Y ^a   Kim, J S ^a   Park, Y J ^a   Hong, J I ^a   Park, J W ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

Alloying; Artificial intelligence; Etching; Filling; Microstructure; Passivation; Random access memory; Temperature; Thermal stresses; Thermomechanical processes

Indexed keywords

ALLOYING; ALUMINUM; ARTIFICIAL INTELLIGENCE; BUDGET CONTROL; ETCHING; FILLING; MICROSTRUCTURE; PASSIVATION; RANDOM ACCESS STORAGE; RELIABILITY; TEMPERATURE; THERMAL STRESS;

ABAQUS SIMULATIONS; ALLOYING PROCESS; HIGH TEMPERATURE STRESS; PASSIVATION MATERIALS; RANDOM ACCESS MEMORY; STRESS ENHANCEMENT; THERMOMECHANICAL PROCESS; VOLUME SHRINKAGE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84949767627     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2001.922917     Document Type: Conference Paper

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