Effective diagnostics through interval unloads in a BIST environment

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 249-254

  Wohl, Peter ^a   Waicukauski, John A ^a   Patel, Sanjay ^a   Maston, Greg ^a  

^a SYNOPSYS INC   (United States)

Author keywords

Built in self test (BIST); Fault diagnosis

Indexed keywords

ALGORITHMS; BUILT-IN SELF TEST; DATA ACQUISITION; LOGIC DESIGN;

ELECTRIC FAULT DIAGNOSIS;

ELECTRIC FAULT LOCATION;

EID: 0036059569     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/513982.513984     Document Type: Conference Paper

References (28)

1. Testing a microprocessor product using a signature analysis
2. A tutorial on built-in self-test, part 1: Principles
3. Self-testing of multichip logic modules
4. A tutorial on built-in self-test, part 2: Applications
5. Automated synthesis of large phase shifters for built-in self-test
6. Automated synthesis of phase shifters for built-in self-test applications
7. Design of compactors for signature-analyzers in built-in self test
8. There is information in faulty signatures
9. Identification of failing tests with cycling registers
10. Fault diagnosis in scan-based BIST using both time and space information
11. A diagnosis method using pseudo-random vectors without intermediate signatures
12. Deterministic partitioning techniques for fault diagnosis in scan-based BIST
13. A rapid and scalable diagnosis scheme for BIST environments with a large number of scan chains
14. Diagnostic techniques for the IBM S/390 600 MHz G5 microprocessor
15. BIST fault diagnosis in scan-based VLSI environments
16. Fault diagnosis in scan-based BIST
17. LFSR-coded test patterns for scan designs
18. Salvaging test windows in BIST diagnostics
19. Diagnosis of BIST failures by PPSFP simulation