Experimental results for slow-speed testing

Proceedings of the IEEE VLSI Test Symposium

Volumn 2002-January, Issue , 2002, Pages 37-42

  Tseng, Chao Wen ^a   Li, J ^a   McCluskey, E J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

Chaos; Circuit faults; Circuit testing; Cyclic redundancy check; Delay; Large scale integration; Logic testing; Manufacturing; Timing; Voltage

Indexed keywords

CHAOS THEORY; ELECTRIC POTENTIAL; LSI CIRCUITS; MANUFACTURE; SPEED; TESTING; TIMING CIRCUITS; VLSI CIRCUITS;

CIRCUIT FAULTS; CIRCUIT TESTING; CYCLIC REDUNDANCY CHECK; DELAY; LOGIC TESTING; TIMING;

INTEGRATION TESTING;

EID: 0142131315     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTS.2002.1011108     Document Type: Conference Paper

References (14)

1. Benowitz, N. et al., "An advanced fault isolation system for digital logic," IEEE Trans. on Computers, vol.C-24, no.5, pp. 489-97, May 1975.
2. Baker, K. et al., "Defect-based Delay Testing of Resistive Vias-Contacts, a Critical Evaluation," Proc. 1999 International Test Conference, pp. 467-476.
3. Chang, J.T.Y. and E.J. McCluskey, "Quantitative Analysis of Very-Low-Voltage Testing," Proc. VLSI Test Symposium, pp. 332-337, 1996.
4. Chang, T.Y.J., C.W. Tseng, Y.C. Chu, S. Wattal, M. Purtell, and E.J. McCluskey, "Experimental Results for IDDQ and VLV Testing," Proc. VLSI Test Symposium, pp. 118-123, 1998
5. Franco, P., R.L. Stokes, W.D. Farwell, and E.J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Part 1: Description of Experiment," CRC TR 94-5.
6. Hao, H., and E.J. McCluskey, "Very-Low-Voltage Testing for Weak CMOS Logic IC's," Proc. International Test Conference, pp. 275-284, 1993.
7. Li, J. C.M., et.al., "ELF35 Experiment - Chip and Experiment Design," TR 99-3, Center for Reliable Computing, Stanford University, 1999.
8. Li, J.C.M., C.W. Tseng, and E.J. McCluskey, "Testing for Resistive Opens and Stuck Opens," 2001 International Test Conference, to appear.
9. Liao, Y. and D.M.H. Walker, "Fault Coverage Analysis for Physically-based CMOS bridging faults at different power supply voltages," Proc. 1996 International Test Conference, pp. 767-775, 1996.
10. McCluskey, E.J. and C.W. Tseng, "Stuck-at Tests vs. Real Defects," Proc. 2000 International Test Conference, pp.336-343, 2000.
11. W. Needham, et. al., "High Volume Microprocessor Test Escapes, An Analysis of Defects Our Tests Are Missing," Proc. 1998 International Test Conference, Baltimore, 1998.
12. Nigh, P. and A. Gattiker, "Test Method Evaluation Experiments and Data," Proc. 2000 International Test Conference, pp.454-463, 2000.
13. Touba, N.A., and E.J. McCluskey, "Alternating a Pseudo-Random Bit Sequence for Scan-Based BIST," Proc. 1996 International Test Conference, pp.167-175, 1996.
14. Tseng, C.W. and E.J. McCluskey, "Multiple Output Propagation Transition Test," Proc. 2001 International Test Conference, 2001