Test Vector Decomposition-Based Static Compaction Algorithms for Combinational Circuits

ACM Transactions on Design Automation of Electronic Systems

Volumn 8, Issue 4, 2003, Pages 430-459

  El Maleh, Aiman H ^a   Osais, Yahya E ^a  

^a KING FAHD UNIVERSITY OF PETROLEUM AND MINERALS   (Saudi Arabia)

Author keywords

Class based clustering; Combinational circuits; Independent fault clustering; Static compaction; Taxonomy; Test vector decomposition

Indexed keywords

ALGORITHMS; COMPACTION; DATA STORAGE EQUIPMENT; SEMICONDUCTOR DEVICE TESTING; SYSTEMS ANALYSIS; VECTORS;

CLUSTERING TECHNIQUES;

COMBINATORIAL CIRCUITS;

EID: 0142095234     PISSN: 10844309     EISSN: None     Source Type: Journal    
DOI: 10.1145/944027.944030     Document Type: Article

References (30)

1. ABRAMOVICI, M., BRUER, M. A., AND FRIEDMAN, A. D. 1990. Digital Systems Testing and Testable Design. IEEE, Piscataway, NJ.
2. ABRAMOVICI, M., MENON, P. R., AND MILLER, D. T. 1984. Critical path tracing - an alternative to fault simulation. IEEE Design Test, 83-92.
3. AKERS, S. B. AND JOSEPH, C. 1987. On the role of independent fault sets in the generation of minimal test sets. In Proceedings of the International Test Conference (Washington, D.C.). IEEE Computer Society Press, Los Alamitos, Calif, 1100-1107.
4. AKERS, S. B., KRISHAMURTHY, B., PARK, S., AND SWAMINATHAN, A. 1990. Why is less information from logic simulation more useful in fault simulation? In Proceedings of the International Test Conference. IEEE, Los Alamitos, Calif, 786-800.
5. AKERS, S. B. AND KRISHNAMURTHY, B. 1989. Test counting: A tool for VLSI testing. IEEE Design Test Comput. 6, 5 (Oct.), 58-73.
6. AYARI, B. AND KAMINSKA, B. 1994. A new dynamic test vector compaction for automatic test pattern generation. IEEE Trans. Computer-Aided Des. Integ. Circ. Syst. 13, 3 (Mar.), 353-358.
7. BOATENG, K. O., KONISHI, H., AND NAKATA, T. 2001. A method of static compaction of test stimuli. In Proceedings of the Asian Test Symposium (Kyoto, Japan). IEEE Computer Society Press, Los Alamitos, Calif., 137-142.
8. CHANG, J.-S. AND LIN, C.-S. 1995. Test set compaction for combinational circuits. IEEE Trans. Computer-Aided Des. Integ. Circ. Syst. 14, 11 (Nov.), 1370-1378.
9. EL-MALEH, A. AND AL-SUWAIYAN, A. 2002. An efficient test relaxation technique for combinational and full-scan sequential circuits. In Proceedings of the VLSI Test Symposium (Monterey, Calif). IEEE Computer Society Press, Los Alamitos, Calif, 53-59.
10. FLORES, P. F., NETO, H. C., AND MARQUES-SILVA, J. P. 1999. On applying set covering models to test set compaction. In Proceedings of the 9th Great Lakes Symposium on VLSI (Ypsilanti, Miss.). IEEE Computer Society Press, Los Alamitos, Calif, 8-11.
11. GAREY, M. R. AND JOHNSON, D. S. 1979. Computers and Intractability: A Guide to the Theory of NP-Completeness. W.H. Freedman, San Francisco.
12. HAMZAOGLU, I. AND PATEL, J. H. 1998. Test set compaction algorithms for combinational circuits. In Proceedings of the International Conference on Computer-Aided Design (San Jose, Calif.). IEEE Computer Society Press, Los Alamitos, Calif., 283-289.
13. HAMZAOGLU, I. AND PATEL, J. H. 2000. Test set compaction algorithms for combinational circuits. IEEE Trans. Computer-Aided Des. Integ. Circ. Syst. 19, 8 (Aug.), 957-963.
14. HOCHBAUM, D. S. 1996. An optimal test compression procedure for combinational circuits. IEEE Trans. Computer-Aided Des. Integ. Circ. Syst. 15, 10 (Oct.), 1294-1299.
15. KAJIHARA, S. AND MIYASE, K. 2001. On identifying don't care inputs of test patterns for combinational circuits. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (San Jose, Calif.). IEEE Computer Society Press, Los Alamitos, Calif., 364-369.
16. KAJIHARA, S., POMERANZ, I., KINOSHITA, K., AND REDDY, S. M. 1994. On compacting test sets by addition and removal of test vectors. In Proceedings of the VLSI Test Symposium (Cherry Hill, N.J.). IEEE Computer Society Press, Los Alamitos, Calif., 25-28.
17. KAJIHARA, S., POMERANZ, I., KINOSHITA, K., AND REDDY, S. M. 1995. Cost effective generation of minimal test sets for stuck-at faults in combinational logic circuits. IEEE Trans. Computer-Aided Des. 14, 12 (Dec.), 1496-1504.
18. KRISHNAMURTHY, B. AND AKERS, S. B. 1984. On the complexity of estimating the size of a test set. IEEE Trans. Comput. C-33, 8 (Aug.), 750-753.
19. LEE, H. K. AND HA, D. S. 1996. HOPE: An efficient parallel fault simulator for synchronous sequential circuits. IEEE Trans. Computer-Aided Des. Integ. Circ. Syst. 15, 9 (Sept.), 1048-1058.
20. LIN, X., RAJSKI, J., POMERANZ, I., AND REDDY, S. M. 2001. On static test compaction and test pattern ordering for scan designs. In Proceedings of the International Test Conference (Baltimore, Md). IEEE Computer Society Press, Los Alamitos, Calif., 1088-1098.
21. MCHUGH, J. 1990. Algorithmic Graph Theory. Prentice-Hall, Englewood Cliffs, N.J.
22. MIYASE, K., KAJIHARA, S., AND REDDY, S. M. 2002. A method of static test compaction based on don't care identification. In Proceedings of the 1st IEEE Intetnational Workshop on Electronic Design, Test, and Application (Christchurch, New Zealand). IEEE Computer Society Press, Los Alamitos, Calif., 392-395.
23. NIERMANN, T. M. AND PATEL, J. H. 1991. HITEC: A test generation package for sequential circuits. In Proceedings of the European Conference on Design Automation (Amsterdam, Netherlands). IEEE Computer Society Press, Los Alamitos, Calif, 214-218.
24. POMERANZ, I., REDDY, L. N., AND REDDY, S. M. 1993. Compacttest: A method to generate compact test sets for combinational circuits. IEEE Trans. Computer-Aided Des. Integ. Circ. Syst. 12, 7 (July), 1040-1049.
25. POMERANZ, I. AND REDDY, S. M. 1992. Generalization of independent faults for transition faults. In Proceedings of the VLSI Test Symposium (Atlantic City, N.J.). IEEE Computer Society Press, Los Alamitos, Calif, 7-12.
26. POMERANZ, I. AND REDDY, S. M. 2001. Forward-looking fault simulation for improved static compaction. IEEE Trans. Computer-Aided Des. Integ. Circ. Syst. 20, 10 (Oct.), 1262-1265.
27. REDDY, L. N., POMERANZ, I., AND REDDY, S. M. 1992. ROTCO: A reverse order test compaction technique. In Proceedings of the EURO-ASIC Conference (Paris, France). IEEE Computer Society Press, Los Alamitos, Calif, 189-194.
28. SCHULZ, M. H., TRISCHLER, E., AND SARFERT, T. M. 1988. SOCRATES: A highly efficient automatic test pattern generation system. IEEE Trans. Computer-Aided Des. Integ. Circ. Syst. 7, 1 (Jan.), 126-137.
29. TROMP, G.-J. 1991. Minimal test sets for combinational circuits. In Proceedings of the International Test Conference. IEEE Computer Society Press, Los Alamitos, Calif., 204-209.
30. WANG, J. C. AND STABLER, E. P. 1995. Collective test generation and test set compaction. In Proceedings of the International Symposium on Circuits and Systems (Seattle, Wash.). IEEE Computer Society Press, Los Alamitos, Calif., 2008-2011.