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Volumn 7, Issue 4, 1999, Pages 477-482

Statistical analysis of timing rules for high-speed synchronous VLSI systems

Author keywords

Random skew; Self timed VLSI systems; Static skew; Synchronous VLSI systems; Timing rules; Timing skew; Wave pipelining

Indexed keywords

MATHEMATICAL MODELS; SPURIOUS SIGNAL NOISE; STATISTICAL METHODS;

EID: 0033280316     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.805754     Document Type: Article
Times cited : (4)

References (14)
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  • 2
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    • Performance of synchronous and asynchronous schemes for VLSI systems
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    • M. Afghani and C. Svensson, "Performance of synchronous and asynchronous schemes for VLSI systems," IEEE Trans. Comput., vol. 41, pp. 858-872, July 1992.
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    • Afghani, M.1    Svensson, C.2
  • 6
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    • Asynchronous and clocked control structures for VLSI based interconnection network
    • Mar.
    • D. F. Wann and M. A. Franklin, "Asynchronous and clocked control structures for VLSI based interconnection network," IEEE Trans. Comput., vol. C-32, pp. 284-293, Mar. 1983.
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    • Wann, D.F.1    Franklin, M.A.2
  • 8
    • 0024771230 scopus 로고
    • Automatic synthesis of asynchronous circuits from high-level specifications
    • Nov.
    • T. H.-Y. Meng, R. W. Brodersen, and D. G. Messerschmitt, "Automatic synthesis of asynchronous circuits from high-level specifications," IEEE Trans. Computer-Aided Design, vol. 8, pp. 1185-1205, Nov. 1989.
    • (1989) IEEE Trans. Computer-Aided Design , vol.8 , pp. 1185-1205
    • Meng, T.H.-Y.1    Brodersen, R.W.2    Messerschmitt, D.G.3
  • 11
    • 0025464163 scopus 로고
    • Clock skew optimization
    • July
    • J. P. Fishburn, "Clock skew optimization," IEEE Trans. Comput., vol. 39, pp. 945-951, July 1990.
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    • Fishburn, J.P.1
  • 12
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    • Clock skew analysis for si and gaas receivers
    • R. L. Khalil, "Clock skew analysis for si and gaas receivers," Proc. SPIE - Int. Soc. Opt. Eng., vol. 1178, pp. 171-176, 1989.
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    • Khalil, R.L.1
  • 13
    • 0025628821 scopus 로고
    • An upper bound on expected clock skew in synchronous systems
    • Dec.
    • S. D. Kugelmass and K. Steiglitz, "An upper bound on expected clock skew in synchronous systems," IEEE Trans. Comput., vol. 39, pp. 1475-1477, Dec. 1990.
    • (1990) IEEE Trans. Comput. , vol.39 , pp. 1475-1477
    • Kugelmass, S.D.1    Steiglitz, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.