Mapping of generalized template matching onto reconfigurable computers

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 11, Issue 3, 2003, Pages 485-498

  Liang, Xuejun ^a   Jean, Jack Shiann Ning ^a  

^a Wright State University   (United States)

Author keywords

Field programmable gate array (FPGA); High level synthesis; Image analysis; Reconfigurable computing; Template matching

Indexed keywords

ALGORITHMS; BUFFER CIRCUITS; DIGITAL FILTERS; IMAGE ANALYSIS; LOGIC DESIGN; MATHEMATICAL MORPHOLOGY; MICROPROCESSOR CHIPS; MOTION ESTIMATION; PARALLEL PROCESSING SYSTEMS; PATTERN MATCHING; SHIFT REGISTERS;

GENERALIZED TEMPLATE MATCHING; HIGH LEVEL SYNTHESIS; RECONFIGURABLE COMPUTERS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0042921360     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2003.812306     Document Type: Article

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