Topography reduction for copper damascene interconnects

Solid State Technology

Volumn 46, Issue 8, 2003, Pages 49-50+52+54

  Stickney, Brian ^a   Nguyen, Bang ^a   Basol, Bulent ^a   Uzoh, Cyprian ^a   Talieh, Homayoun ^a  

^a NuTool Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; DEPOSITION; ELECTRIC RESISTANCE; INTERCONNECTION NETWORKS; SILICON WAFERS; SURFACE TOPOGRAPHY;

DAMASCENE INTERCONNECTS; DISHING; TOMOGRAPHY REDUCTION;

COPPER;

EID: 0042886050     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (10)

1. S. Hymens et al., "Evolution of Topography During 1st Step CMP of Cu-Plated Damascene Structures," Electrochemical Society CMP Symposium, Oct. 1999.
2. T. Park et al., "Multi-Level Pattern Effects in Copper CMP," Electrochemical Society CMP Symposium, Oct. 1999.
3. K.C. Yu et al., "Integration Challenges of 0.1μm CMOS Cu/Low-k Interconnects," IITC 2002.
4. G. Banerjee, J. So, B. Mikkola, "Simultaneous Optimization of Electroplating and CMP for Copper Process," Solid State Technology, November 2001.
5. T.I. Bao et al., "90nm Generation Cu/CVD Low-k (k<2.5) Interconnect Technology," IEDM 2002.
6. S. Lakshimnarayanan, P. Wright, J. Pallinti, "Design Rule Methodology to Improve the Manufacturability of the Copper CMP Process," IITC 2002.
7. B. Basol et al., "ECMD Technique for Semiconductor Interconnect Applications," Microelectronic Engineering, Vol. 64, p. 43, 2002.
8. www.xinitiative.org.
9. W.S. Shue et al., "CMP-Free and CMP-Less Approaches for Multilevel Cu/Low-k BEOL Integration," IEDM 2001.
10. T. Nogami et al., "Newly Developed Electro-Chemical Polishing Process of Copper as Replacement of CMP Suitable for Damascene Copper Inlaid in Fragile Low-k Dielectrics," IEDM 2001.