Extended 90 nm CMOS technology with high manufacturability for high-performance, low-power, RF/analog applications

Fujitsu Scientific and Technical Journal

Volumn 39, Issue 1, 2003, Pages 32-39

  Takao, Yoshihiro ^a   Nakai, Satoshi ^a   Horiguchi, Naoto ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; ELECTRIC CONTACTS; ELECTRIC INDUCTORS; ELECTRIC POWER SUPPLIES TO APPARATUS; MASKS; MIM DEVICES; POWER ELECTRONICS; RELIABILITY; SEMICONDUCTOR DEVICE STRUCTURES; STATIC RANDOM ACCESS STORAGE;

INTERLAYER DIELECTRIC; POWER TRANSISTOR;

INTEGRATED CIRCUIT LAYOUT;

EID: 0042698822     PISSN: 00162523     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (7)

1. T. Ghani et al.: 100nm gate length high performance/low power CMOS transistor structure. International Electron Devices Meeting 1999, December 5-8, 1999, Washington DC, p. 415-418.
2. T. Skotnicki et al.: Well-controlled, selectively under-etched Si/SiGe gates for RF and high performance CMOS. 2000 Symposium on VLSI Technology, June 13-15, 2000, Honolulu, p. 156-157.
3. G. C-F Yeap et al.: A 100nm copper/low-k bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications. 2002 Symposium on VLSI Technology, June 11-13, 2002, Honolulu, p. 16-17.
4. S. Nakai et al.: A 100nm CMOS technology with "sidewall-notched" 40nm transistors and SiC-capped Cu/VLK interconnects for high performance microprocessor applications. 2002 Symposium on VLSI Technology, June 11-13, 2002, Honolulu, p.66-67.
5. Y. Takao et al.: 0.65V device design with high-performance and high-density 100nm CMOS technology for low operation power application. 2002 Symposium on VLSI Technology, June 11-13, 2002, Honolulu, p.122-123.
6. Y. Takao et al.: A 0.11μm CMOS technology featuring copper and very low k interconnects with high performance and reliability. Microelectronics reliability, 42, p. 15-25 (2002).
7. K. Suzuki et al.: A strategy using a copper/low-k BEOL process to prevent negative-bias temperature instability (NBTI) in p-MOSFETs with ultra-thin gate oxide. 2002 Symposium on VLSI Technology, June 11-13, 2002, Honolulu, p.216-217.