메뉴 건너뛰기




Volumn , Issue , 2000, Pages 156-157

Well-controlled, selectively under-etched Si/SiGe gates for RF and high performance CMOS

Author keywords

[No Author keywords available]

Indexed keywords

GATES (TRANSISTOR); SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS; TRANSCONDUCTANCE;

EID: 0033682137     PISSN: 07431562     EISSN: None     Source Type: Journal    
DOI: 10.1109/VLSIT.2000.852807     Document Type: Article
Times cited : (9)

References (8)
  • 1
    • 17344376740 scopus 로고    scopus 로고
    • 100nm gate length high performance/low power CMOS transistor structure
    • A. Ghani 100nm gate length high performance/low power CMOS transistor structure IEDM 1999 415 418 IEDM 1999
    • Ghani, A.1
  • 2
    • 0032123912 scopus 로고    scopus 로고
    • Investigation of Poly-Si1-xGex for dual-gate CMOS technology
    • C. Hu Investigation of Poly-Si1-xGex for dual-gate CMOS technology IEEE EDL 19 7 247 249 1998
    • (1998) IEEE EDL , vol.19 , Issue.7 , pp. 247-249
    • Hu, C.1
  • 3
    • 0028374842 scopus 로고
    • Electrical properties of heavily doped polycristalline SiGe films
    • T. King Electrical properties of heavily doped polycristalline SiGe films IEEE TED 41 2 228 232 1994
    • (1994) IEEE TED , vol.41 , Issue.2 , pp. 228-232
    • King, T.1
  • 4
    • 84886448090 scopus 로고    scopus 로고
    • Gate-workfunction engineering using poly-SiGe for high performance 0.18μm CMOS technology
    • Y. Ponomariev Gate-workfunction engineering using poly-SiGe for high performance 0.18μm CMOS technology IEDM 1997 829 832 IEDM 1997
    • Ponomariev, Y.1
  • 5
    • 85177107529 scopus 로고    scopus 로고
    • Symetric CMOS in fully depleted SOI P+ polycristalline SiGe gate
    • N. Kistler J. Woo Symetric CMOS in fully depleted SOI P+ polycristalline SiGe gate IEDM 1993 727 730 IEDM 1993
    • Kistler, N.1    Woo, J.2
  • 6
    • 84886447961 scopus 로고    scopus 로고
    • CMOS devices below 0.1μm: how high will performance go?
    • Y. Taur E. Nowak CMOS devices below 0.1μm: how high will performance go? IEDM 1997 215 218 IEDM 1997
    • Taur, Y.1    Nowak, E.2
  • 7
    • 0033280988 scopus 로고    scopus 로고
    • SON (Sillicon-On-Nothing)-a new device architecture for the ULSI era
    • M. Jurczak SON (Sillicon-On-Nothing)-a new device architecture for the ULSI era 1999 Symp. VLSI Techn. 29 30 1999 Symp. VLSI Techn.
    • Jurczak, M.1
  • 8
    • 0031636458 scopus 로고    scopus 로고
    • S/D extension scaling for 0.1μm and below channel length MOSFETs
    • S. Thompson S/D extension scaling for 0.1μm and below channel length MOSFETs 1998 Symp. VLSI Techn. 132 133 1998 Symp. VLSI Techn.
    • Thompson, S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.