Analytical solutions to the one-dimensional oxide-silicon-oxide system

IEEE Transactions on Electron Devices

Volumn 50, Issue 8, 2003, Pages 1793-1800

  Shi, Xuejie ^a   Wong, Man ^a  

^a HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

Analytical solution; Double gate (DG); Metal oxide semiconductor capacitor; Oxide silicon oxide; Silicon on insulator (SOI)

Indexed keywords

ELECTRIC FIELDS; GATES (TRANSISTOR); MOS CAPACITORS; SILICON ON INSULATOR TECHNOLOGY;

DOUBLE-GATE (DG);

SILICON COMPOUNDS;

EID: 0042026582     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.815138     Document Type: Article

References (12)

1. J. P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI. Boston, MA: Kluwer, 1991.
2. H.-S. P. Wong, K. K. Chan, and Y. Taur, "Self-aligned (top and bottom) double-gate MOSFET with a 25-nm thick silicon channel," in Proc. Int. Electron Device Meet., 1997, pp. 427-430.
3. S. Tang, L. Chang, N. Lindert, Y.-K. Choi, W.-C. Lee, X. Huang, V. Subramanian, J. Bokor, T.-J. King, and C. Hu, "FinFET - a quasiplanar double-gate MOSFET." in ISSCC Tech. Dig., 2001, pp. 118-119.
4. 4 double-gate SOI MOSFET's," IEEE Trans. Electron Devices, vol. 43, pp. 732-738, May 1996.
5. + double-gate SOI MOSFET's," IEEE Trans. Electron Devices, vol. 42, pp. 1940-1948, Oct. 1995.
6. Y. Taur, "Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs," IEEE Trans. Electron Devices, vol. 48, pp. 2861-2869, Dec. 2001.
7. H.-S. P. Wong and Y. Taur, "Three-dimensional 'atomistic' simulation of discrete microscopic random dopant distributions effects in Sub-0.1 μm MOSFET's," in Proc. Int. Electron Devices Meet., 1993, pp. 705-708.
8. L. Ge and J. G. Jerry G. Fossum, "Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFET's," IEEE Trans. Electron Devices, vol. 49, pp. 287-294, Feb. 2002.
9. G. Baccarani and S. Reggiani, "A compact double-gate MOSFET model comprising quantum-mechanical and nonstatic effects," IEEE Trans. Electron Devices, vol. 46, pp. 1656-1666, Aug. 1999.
10. A. Yagishita, T. Saito, S. Inumiya, K. Matson, Y. Tsunashima, and K. Suguro, "Dynamic threshold voltage damascene metal gate MOSFET (DT-DMG-MOS) technology for very low voltage operation of under 0.7 V," IEEE Trans. Electron Devices, vol. 49, pp. 422-428, Mar. 2002.
11. Z. Meng, M. Wang, and M. Wong, "High performance low temperature metal-induced unilaterally crystallized polycrystalline silicon thin film transistor for system-on-panel applications," IEEE Trans. Electron Devices, vol. 47, pp. 404-409, Feb. 2000.
12. H.-S. P. Wong, D. J. Frank, and P. M. Solomon, "Device design considerations for double-gate, ground plane and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation," in Proc. Int. Electron Device Meet., 1998, pp. 407-410.