"Copper chip" technology

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 3509, Issue , 1998, Pages 8-18

  Edelstein, D C ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COPPER; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC WIRING; MICROPROCESSOR CHIPS; MOSFET DEVICES; NUMERICAL METHODS; RELIABILITY; STATIC RANDOM ACCESS STORAGE; ULSI CIRCUITS; ELECTRIC INDUCTORS; METALLIZING; SEMICONDUCTING SILICON; WIRELESS TELECOMMUNICATION SYSTEMS; APPROXIMATION THEORY; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC GATES;

CLOCK SKEW; COPPER CHIP TECHNOLOGY; COPPER WIRING; COPPER CHIPS; CMOS ULSI DEVICE; COPPER METALLIZATION; COPPER ON-CHIP WIRING;

MICROELECTRONIC PROCESSING; CMOS INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS;

EID: 0038748374     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.324408     Document Type: Conference Paper

References (17)

1. D. Edelstein et al., "Full Copper Wiring in a Sub-0.25 μm CMOS ULSI Technology", Tech. Digest IEEE Intern. Electron Devices Mtg., pp.773-776 (1997).
2. L. Su, et al., "A High-Performance Sub-0.25 μm CMOS Technology with Multiple Thresholds and Copper Interconnects", Tech. Digest IEEE Symp. VLSI, 18 (1998).
3. D, C. Edelstein, "Advantages of Copper Interconnects", Proc. VLSI Mult. Inter. Conf., 12, 301 (1995)
4. D. C. Edelstein, G. A. Sai-Halasz, and Y.-J. Mii "VLSI On-Chip Interconnection Performance Simulations and Measurements", IBM J. Res. Devel. 39, 383 (1995).
5. C.-K. Hu, K. Y. Lee, C. Uzoh, K. Chan, S. Rossnagel, L. Gignac, P. Roper, and J. M. E. Harper, "Extendability of Cu Damascene to 0.1 μm Wide Interconnections", Proc. Symp. Mat. Res. Soc. 507 (to be published, 1998).
6. L. Gwennap, "IC Makers Confront RC Limitations", Microproc. Report, 11, 14 (1997).
7. Philip J. Restle and Alina Deutsch, "Designing the Best Clock Distribution Network", Tech. Digest IEEE Symp. VLSI Circuits, 2 (1998).
8. eff CMOS Technology with Copper Interconnects", Proc. IEEE Int. Sol.-State Circuits Conf., 240 (1998).
9. S. Subbanna, et al., Tech. Digest IEEE Int. Electron Devices Mtg., 275 (1996).
10. L. Su, et al., "A High-Performance 0.08 μm CMOS", Digest IEEE Symp. VLSI Tech., 12 (1996).
11. A. K. Stamper, M. B. Fuselier, and X. Tian, "Advanced Wiring RC Delay Issues for Sub-0.25 μm Generation CMOS", Proc. IEEE Intern. Interconnect Tech. Conf., 62 (1998).
12. A. Deutsch, H. Harrer, C. W. Surovic, G. Hellner, D. C. Edelstein, R. D. Goldblatt, G. A. Biery, N. A. Greco, D. M. Foster, L. T. Su, E. Crabbe, and P. W. Coteus, "Functional High-Speed Characterization and Modeling of a Six-Layer Copper Wiring Structure and Performance Comparison with Aluminum On-Chip Interconnections" IEEE Intern. Electr. Dev. Conf. (to be published, 1998).
13. C.-K. Hu, K. P. Rodbell, T. D. Sullivan, K. Y. Lee, and D. P. Bouldin "Electromigration and Stress-Induced Voiding in Fine Al and Al-Alloy Thin-Film Lines", IBM J. Res. Devel. 39, 465 (1995).
14. J. D. Mc Brayer, R. M. Swanson, and T. Sigmon, "Diffusion of Metals in Silicon Dioxide", J. Electrochem. Soc. 133, 1242 (1986).
15. W. Cote, G. Costrini, D. Edelstein, C. Osborn, D. Poindexter, V. Sardesai, and G. Bronner, "An Evaluation of Cu Wiring in a Production 64Mb DRAM", Tech. Digest IEEE Symp. VLSI Tech., 24 (1998).
16. Joachim N. Burghartz, Daniel C. Edelstein, Keith A. Jenkins, and Young H. Kwark, "Spiral Inductors and Transmission Lines in Silicon Technology Using Copper-Damascene Interconnects and Low-Loss Substrates", IEEE Trans. Micr. Theory Tech. 45, 1961 (1997).
17. Daniel C. Edelstein and Joachim N. Burghartz, "Spiral and Solenoidal Inductor Structures on Silicon Using Cu-Damascene Interconnects", Proc. IEEE Intern. Interconnect Tech. Conf., 18. (1998).