ALPS: An automatic layouter for pass-transistor cell synthesis

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 1998, Pages 227-232

  Sasaki, Yasuhiko ^a   Rikino, Kunihito ^a   Yano, Kazuo ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; GRAPH THEORY; INTEGRATED CIRCUIT LAYOUT; SEMICONDUCTOR DEVICE STRUCTURES;

PASS-TRANSISTOR CELLS;

LOGIC CIRCUITS;

EID: 0032218679     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (9)