Low-power circuit design techniques for multimedia CMOS VLSIs

Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)

Volumn 81, Issue 9, 1998, Pages 67-74

  Kuroda, Tadahiro ^a   Sakurai, Takayasu ^b  

^a TOSHIBA CORPORATION   (Japan)

^b INSTITUTE OF INDUSTRIAL SCIENCE   (Japan)

Author keywords

Low power; Low voltage; Multimedia; Pass transistor logic

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

PASS TRANSISTOR LOGIC;

VLSI CIRCUITS;

EID: 0032169243     PISSN: 10420967     EISSN: None     Source Type: Journal    
DOI: 10.1002/(sici)1520-6440(199809)81:9<67::aid-ecjc8>3.0.co;2-w     Document Type: Article

References (31)

1. T. Kuroda and T. Sakurai. Overview of low-power ULSI circuit techniques. IEICE Trans, on Electronics, E78-C, No. 4, pp. 334-344 (Apr. 1995).
2. S. Mutoh et al. 1 V high-speed digital circuit technology with 0.5 μm multi-threshold CMOS. Proc. IEEE ASIC Conf., pp. 186-189 (1993).
3. 2 2-D discrete cosine transform core processor with variable-threshold-voltage scheme. ISSCC Dig. Tech. Papers, pp. 166-167 (Feb. 1996).
4. T. Kobayashi and T. Sakurai. Self-adjusting threshold-voltage scheme (SATS) for low-voltage highspeed operation. Proc. IEEE ClCC, pp. 271-274 (May 1994).
5. T. Kuroda et al. A high-speed low-power 0.3 μm CMOS gate array with variable threshold voltage (VT) scheme. Proc. IEEE CICC, pp. 53-56 (May 1996).
6. T. Kuroda et al. Substrate noise influence on circuit performance with variable threshold voltage (VT) scheme. Proc. IEEE ISLPED, pp. 309-312 (Aug. 1996).
7. K. Seta et al. 50% active power saving without speed degradation using standby power reduction (SPR) circuit. ISSCC Dig. Tech. Papers, pp. 318-319 (Feb. 1995).
8. K. Yano et al. A 3.8-ns CMOS 16 × 16-b multiplier using complementary pass-transistor logic. IEEE J. Solid-State Circuits, 25, No. 2, pp. 388-395 (Apr. 1990).
9. F.S. Lai and W. Hwang. Differential cascade voltage switch with the pass-gate (DCVSPG) logic tree for high performance CMOS digital systems. Proc. IEEE VLSI-TSA, pp. 358-362 (1993).
10. A. Parameswar, H. Hara, and T. Sakurai. A highspeed, low-power, swing restored pass-transistor logic based multiply and accumulate circuit for multimedia applications. Proc. IEEE CICC, pp. 278-281 (May 1994).
11. T. Sakurai, B. Lin, and A.R. Newton. Multiple-output shared transistor logic (MOSTL) family synthesized using binary decision diagram. Dept. EECS, Univ. Of Calif., Berkeley, ERL Memo M90/21 (Mar. 1990).
12. M. Matsui et al. 200 MHz video compression macrocells using low-swing differential logic. ISSCC Dig. Tech. Papers, pp. 76-77 (Feb. 1994).
13. K. Yano, Y. Sasaki, K. Rikino, and K. Seki. Lean integration: achieving a quantum leap in performance and cost of logic LSIs. Proc. IEEE CICC, pp. 603-606 (May 1994); Top-down pass-transistor logic design. IEEE J. of Solid-State Circuits, 31, No. 6, pp. 792-803 (June 1996).
14. K. Yano, Y. Sasaki, K. Rikino, and K. Seki. Lean integration: achieving a quantum leap in performance and cost of logic LSIs. Proc. IEEE CICC, pp. 603-606 (May 1994); Top-down pass-transistor logic design. IEEE J. of Solid-State Circuits, 31, No. 6, pp. 792-803 (June 1996).
15. A.J. Stratakos, R.W. Brodersen, and S.R. Sanders. High-efficiency low-voltage DC-DC conversion for portable applications. Proc. IEEE IWLPD, pp. 105-110 (Apr. 1994).
16. L.R. Carley and I. Lys. QuadRail: A design methodology for ultra-low power ICs. Proc. IEEE IWLPD, pp. 225-230 (Apr. 1994).
17. H. Kojima, S. Tanaka, and K. Sasaki. Half-swing clocking scheme for 75% power saving in clocking circuitry. Proc. IEEE Symposium on VLSI Circuits, pp. 23-24 (May 1994).
18. A. Chandrakasan, A. Burstein, and R.W. Brodersen. A low power chipset for portable multimedia applications. ISSCC Dig. Tech. Papers, pp. 82-83 (Feb. 1994).
19. H. Yamauchi, H. Akamatsu, and T. Fujita. A low power complete charge-recycling bus architecture for ultra-high data rate ULSI's. Proc. IEEE 1994 Symposium on VLSI Circuits, pp. 21-22 (May 1994).
20. C. Lemonds and S.S.M. Shetti. A low power 16 by 16 multiplier using transition reduction circuitry. Proc. IEEE IWLPD, pp. 139-142 (Apr. 1994).
21. S.C. Prasad and K. Roy. Circuit optimization for minimization of power consumption under delay constraint. Proc. IEEE IWLPD, pp. 15-20 (Apr. 1994).
22. C.H. Tan and J. Allen. Minimization of power in VLSI circuits using transistor sizing, input ordering, and statistical power estimation. Proc. IEE IWLPD, pp. 75-80 (Apr. 1994).
23. M. Yamadaet al. Synergistic power/area optimization with transistor sizing and write length minimization. Proc. IEEE Symposium on Low Power Electronics (Oct. 1994).
24. M. Mizuno et al. A GHz MOS adaptive pipeline technique using variable delay circuits. Proc. IEEE Symposium on VLSI Circuits, pp. 27-28 (May 1994).
25. T. Sakurai. High-speed circuit design with scaleddown MOSFET's and low supply voltage. Proc. IEEE ISCAS, pp. 1487-1490 (May 1993).
26. M. Horiguchi, T. Sakata, and K. Itoh. Switchedsource-tmpedance CMOS circuit for low standby subthreshold current giga-scale LSIs. Proc. IEEE Symposium on VLSI Circuits, pp. 47-48 (May 1993).
27. Q. Zhu et al. Low power clock distribution based on area pad interconnect for multichip modules. Proc. IEEE IWLPD, pp. 87-92 (Apr. 1994).
28. B. Gunning et al. A CMOS low-voltage-swing transmission-line transceiver. ISSCC Dig. Tech. Papers, pp. 58-59 (Feb. 1992).
29. K. Nogami and A.E. Gamal. A CMOS 160 Mb/s phase modulation I/O interface circuit. ISSCC Dig. Tech. Papers, pp. 108-109 (Feb. 1994).
30. T. Kawahara et al. Low power chip interconnection by dynamic termination. Proc. IEEE Symposium on VLSI Circuits, pp. 45-46 (May 1994).
31. T. Sakurai and T. Kuroda. Low-power circuit design for multimedia CMOS VLSIs. Proc. Sasimi Workshop, pp. 3-10 (Nov. 1996).