CMOS compatibility of high aspect ratio micromachining (HARM) in bonded silicon on insulator (BSOI)

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 3511, Issue , 1998, Pages 277-285

  McNie, M E ^a   King, D O ^a  

^a DEFENCE SCIENCE AND TECHNOLOGY LABORATORY   (United Kingdom)

Author keywords

CMOS compatible; HARM; Inertial; Low temperature; Micromachining; Process; Silicon; SOI

Indexed keywords

CAPACITORS; CMOS INTEGRATED CIRCUITS; DEPOSITION; DRY ETCHING; MICROMACHINING; OPTIMIZATION; PHOTOLITHOGRAPHY; SILICON ON INSULATOR TECHNOLOGY; TEMPERATURE; TRANSISTORS;

CMOS TRANSISTOR; CMOS WAFERS; DEEP DRY ETCHING;

MICROELECTRONIC PROCESSING;

EID: 0037998356     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.324311     Document Type: Conference Paper

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