Propagation delay model of a current driven RC chain for an optimized design

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 50, Issue 4, 2003, Pages 572-575

  Palumbo, Gaetano ^a   Poli, Massimo ^a  

^a UNIVERSITY OF CATANIA   (Italy)

Author keywords

Propagation delay; RC chains; Transmission gates; Very large scale integration (VLSI)

Indexed keywords

APPROXIMATION THEORY; CMOS INTEGRATED CIRCUITS; ELECTRIC CURRENTS; ELECTRIC POWER UTILIZATION; OPTIMIZATION; SILICON; WAVE PROPAGATION;

CURRENT GENERATORS;

DELAY CIRCUITS;

EID: 0037936546     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2003.809805     Document Type: Article

References (25)

1. J. Rabaey, Digital Integrated Circuits (A Design Perspective). Englewood Cliffs, NJ: Prentice-Hall, 1996.
2. N. Weste and K. Eshraghian, Principles of CMOS VLSI Design (A System Perspective), 2nd ed. Reading, MA: Addison-Wesley, 1994.
3. S. Kang and Y. Leblebici, CMOS Digital Integrated Circuits, 2nd ed. New York: McGraw-Hill, 1999.
4. J. Uyemura, CMOS Logic Circuit Design. Norwell, MA: Kluwer, 1999.
5. K. Martin, Digital Integrated Circuit Design. Oxford, U.K.: Oxford Univ. Press, 2000.
6. A. Chandrakasan, W. Bowhill, and F. Fox, Eds., Design of High-Performance Microprocessor Circuits. Piscataway, NJ: IEEE Press, 2001.
7. R. Ho, K. Mai, and M. Horowitz, "The future of wire," Proc. IEEE, vol. 89, pp. 490-504, Apr. 2001.
8. F. Caignet, S. Delmas-Bendhia, and E. Sicard, "The challenge of signal integrity in deep-submicrometer CMOS technology," Proc. IEEE, vol. 89, pp. 556-573, Apr. 2001.
9. D. Sylvester and K. Keutzer, "Impact of small process geometries on microarchitectures in systems on a chip," Proc. IEEE, vol. 89, pp. 467-489, Apr. 2001.
10. N. Menezes and L. Pileggi, "Analyzing on-chip interconnect effects," in Design of High-Performance Microprocessor Circuits, A. Chandrakasan, W. Bowhill, and F. Fox, Eds. Piscataway, NJ: IEEE Press, 2001, pp. 331-351.
11. X. Zeng and D. Zhou, "Design of GHz VLSI clock distribution circuit," in Proc. IEEE ISCAS 2001, Sydney, Australia, June 2001, pp. V/391-V/394.
12. E. Friedman, "Clock distribution networks in synchronous digital integrated circuits," Proc. IEEE, vol. 89, pp. 665-692, May 2001.
13. V. Adler and E. Friedman, "Uniform repeater insertion in RC trees," IEEE Trans. Circuits Syst. I, vol. 47, pp. 1515-1522, Oct. 2000.
14. C. Alpert, A. Devgan, and C. Kashyap, "RC delay metrics for performance optimizations," IEEE Trans. Computer-Aided Design, vol. 20, pp. 571-582, May 2001.
15. Y. Ismail and E. Friedman, "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits," IEEE Trans. VLSI, vol. 8, pp. 195-206, Apr. 2000.
16. J. Rubinstein, P. Penfield, Jr., and M. A. Horowitz, "Signal delay in RC tree networks," IEEE Trans. Computer-Aided Design, vol. CAD-2, pp. 202-211, July 1983.
17. T. Sakurai, "Approximation of wiring delay in MOSFET LSI," IEEE J. Solid-State Circuits, vol. SC-18, pp. 418-426, July 1983.
18. J. L. Wyatt, Jr., "Signal delay in RC mesh networks," IEEE Trans. Circuits Syst., vol. CAS-32, pp. 507-510, May 1985.
19. J. L. Wyatt, Jr., C. A. Zukowski, and P. Penfield, Jr., "Step response bounds for system described by M-matrices, with application to timing analysis of digital MOS circuits," in Proc. 24th Conf. Decision and Control, Dec. 1985.
20. D. Standley and J. L. Wyatt, Jr., "Improved signal delay bounds for RC tree networks," Massachusetts Institute of Technology, Cambridge, MA, VLSI Memo no. 86-317, May 1986.
21. J. L. Wyatt, Jr., "Signal propagation delay in RC models for interconnect," in Circuit Analysis, Simulation and Design, A. Ruehli, Ed. Amsterdam, The Netherlands: North-Holland, 1987, vol. 3.
22. W. C. Elmore, "The transient response of damped linear networks with particular regard to wideband amplifiers," J. Appl. Phys., vol. 19, pp. 55-63, 1948.
23. C. Desoer and E. Kuh, Basic Circuit Theory. New York: McGraw-Hill, 1969.
24. D. Auvergne et al., "Delay time evaluation in ED MOS logic LSI," IEEE J. Solid-State Circuits, vol. SC-21, pp. 337-343, Apr. 1986.
25. D. Deschacht, M. Robert, and D. Auvergne, "Explicit formulation of delays in CMOS data path," IEEE J. Solid-State Circuits, vol. 23, pp. 1257-1264, Oct. 1988.