Design of GHz VLSI clock distribution circuit

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 5, Issue , 2001, Pages 391-394

  Zeng, X ^a   Zhou, D ^b  

^a FUDAN UNIVERSITY   (China)

^b UNIVERSITY OF TEXAS AT DALLAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; INTEGRATED CIRCUIT DESIGN; TIMING CIRCUITS; TREES (MATHEMATICS); VLSI CIRCUITS; ALGORITHMS; BUFFER CIRCUITS; MICROPROCESSOR CHIPS; ROUTERS;

BUFFER INSERTION; CLOCK CIRCUITS; CLOCK DISTRIBUTION; CLOCK SIGNAL; GHZ FREQUENCIES; OPTIMAL ALGORITHM; PLANAR TREE; SIGNAL INTEGRITY;

MICROWAVE CIRCUITS; VLSI CIRCUITS;

CLOCK DISTRIBUTION CIRCUITS;

EID: 0035006187     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iscas.2001.922067     Document Type: Conference Paper

References (5)

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3. G. E. Tellez and M. Sarrafzadeh, "Minimal Buffer Insertion in Clock Trees with Skew and Slew Rate Constraints", IEEE Trans, on CAD, vol.16, No.4, pp. 333-342, 1997.
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5. Jan M. Rabaey, "Digital Integrated Circuits", Prentice Hall Electronics and VLSI Series, 1996.