A new method to characterize border traps in submicron transistors using hysteresis in the drain current

IEEE Transactions on Electron Devices

Volumn 50, Issue 4, 2003, Pages 973-979

  ManjulaRani, K N ^a   Rao, V Ramgopal ^a   Vasi, Juzer ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

Author keywords

Border traps; Hysteresis; Silicon nitride; Tunneling

Indexed keywords

CAPACITANCE; CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CURRENTS; ELECTRON TRAPS; ELECTRON TUNNELING; ENERGY GAP; FERMI LEVEL; HYSTERESIS; SILICON NITRIDE; STRESSES; THRESHOLD VOLTAGE; TRANSIENTS;

DRAIN CURRENTS;

FIELD EFFECT TRANSISTORS;

EID: 0037818424     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.812101     Document Type: Article

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