Measurement of plasma etch damage by a new slow trap profiling technique

IEEE Electron Device Letters

Volumn 17, Issue 11, 1996, Pages 515-517

  Tanner, Philip ^b   Dimitrijev, Sima ^a,b   Yeow, Yew Tong ^a,b   Harrison, H Barry ^b  

^a IEEE

^b GRIFFITH UNIVERSITY   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

GATE VOLTAGE; PLASMA ETCH DAMAGE; PLASMA OVERETCH; SLOW TRAP PROFILING TECHNIQUE;

CAPACITORS; FERMI LEVEL; GATES (TRANSISTOR); INTERFACES (MATERIALS); MONITORING; PLASMA ETCHING; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; SILICA;

MOS DEVICES;

EID: 0030284602     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.541766     Document Type: Article

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