Slicing floorplans with boundary constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 18, Issue 9, 1999, Pages 1385-1389

  Young, F Y ^a   Wong, D F ^a   Yang, Hannah H ^a  

^a University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BENCHMARKING; BOUNDARY CONDITIONS; CONSTRAINT THEORY; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; SIMULATED ANNEALING;

BOUNDARY CONSTRAINTS; SLICING FLOORPLAN ALGORITHMS;

VLSI CIRCUITS;

EID: 0032595824     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.784129     Document Type: Article

References (12)

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