Applications of single-wafer rapid-thermal processing to the manufacture of advanced flash memory

IEEE Transactions on Semiconductor Manufacturing

Volumn 16, Issue 2, 2003, Pages 128-137

  Chen, Kuang Chao ^a   Shih, Hsueh Hao ^a   Hwang, Yaw Lin ^a   Hsueh, Cheng Chen ^a   Chung, Henry ^a   Pan, Sam ^a   Lu, Chih Yuan ^a  

^a MACRONIX INTERNATIONAL CO LTD   (Taiwan)

Author keywords

Flash; Floating gate; Reliability; Single wafer processing (SWP); Tunnel oxide

Indexed keywords

CHEMICAL VAPOR DEPOSITION; DIFFUSION; OXIDATION; POLYSILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS;

SINGLE-WAFER PROCESSING;

FLASH MEMORY;

EID: 0037616415     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2003.810942     Document Type: Article

References (28)

1. D. W. Reed and S. D. Leeke, "Industry and MMST program overview," TI Tech. J., vol. 9, no. 5, 1992.
2. P. Singer, "The thinking behind today's cluster tools," Semiconduct. Int., vol. 16, no. 9, pp. 46-51, 1993.
3. K. Saraswat, S. Wood, J. Plummer, and P. Loslcben, "Programmable factory for adaptable IC manufacturing," in Symp. VLSI Technol Tech. Dig. Papers, Kyoto, Japan, May 1993, pp. 131-132.
4. B. C. Cole, "Getting to the market on time," Electron., pp. 62-67, Apr. 1989.
5. K. Derbyshire, "Applications of integrated processing," Solid Stale Technol., vol. 37, no. 12, pp. 45-49, 1994.
6. L. M. Wein, "On the relationship between yield and cycle time in semiconductor wafer fabrication," IEEE Trans. Semiconduct. Manufact., vol. 5, pp. 156-158, May 1992.
7. D. B. Davis, "Beating the clock," Electron. Bus., pp. 21-28, May 29, 1989.
8. D. J. Miller, "Simulation of a semiconductor manufacturing line," Commun. ACM, vol. 33, no. 10, pp. 98-108, 1990.
9. K. C. Chen, H. H. Shih, C. Hsueh, H. Chung, S. Pam, and C. Y. Lu, "Cycle time and process improvement by single wafer thermal processing in production environment," in 10th IEEE Int. Conf. Advanced Thermal Processing of Semiconductors, 2002, pp. 171-176.
10. P. C. Fazan and V. K. Mathews, "A highly manufacturable trench isolation process for deep submicron DRAM's," in IEDM Tech. Dig., 1993, pp. 57-60.
11. B. H. Roh, C. S. Yoon, D. U. Choi, M. J. Kim, D. W. Ha, K. N. Kim, and J. W. Park, "Shallow trench isolation for enhancement of data retention times in giga-bit DRAM," in SSDM'96, Tech. Dig., 1996, pp. 830-832.
12. K. Ryoo, R. Drosd, and W. Wood, "Location effects of extended defects on electrical properties of P+ -n junction," J. Electrochem. Soc., vol. 136, no. 3, pp. 768-771, Mar. 1989.
13. S. Ikeda, Y. Hagiwara, H. Miura, and H. Ohta, "The impact of mechanical stress control on VLSI fabrication process," in IEDM Tech. Dig., 1997, pp. 77-80.
14. J. F. Ziegler, Ion Implantation Science and Technology, 2nd ed. San Diego, CA: Academic, 1988.
15. G. Ghidini, M. Tosi, and C. Clementi, "Feasibility of steam tunnel oxide for advanced non volatile memories," Solid-State Electron., vol. 41, no. 7, pp. 975-979, 1997.
16. J. D. Choi, J. H. Lee, W. H. Lee, K. S. Shin, Y. S. Yim, J. D. Lee, Y. C. Shin, S. N. Chang, K. C. Park, J. W. Park, and C. G. Hwang, "A 0.15 um NAND flash technology with 0.11 μm 2 cell size for 1 Gbit flash memory," in IEDM Tech. Dig., 2000, pp. 767-770.
17. S. Lai, "Where we are and where we are going," in IEDM Tech. Dig., 1998, pp. 971-973.
18. D. Ielmini, A. S. Spinelli, A. L. Lacaita, and A. Modelli, "A statistical model for SILC in flash memories," IEEE Trans. Electron Devices, vol. 49, pp. 1955-1961, Nov. 2002.
19. C. M. Yih, Z. H. Ho, M. S. Liang, and S. S. Chung, "Characterization of hot-hole injection induced SILC and related disturbs in flash memories," IEEE Trans. Electron Devices, vol. 48, pp. 300-306, Feb. 2001.
20. J. Yugami and T. Mine, "A novel nm-grain Poly-Si gate structure for reduction of cell to cell write/erase tunnel current deviation in high speed quarter micron flash memories," in 1997 Symp. VLSI Tech., 1997, pp. 115-116.
21. F. Nkanash, M. Hatalies, and K. Olasupo, "Characterization and modeling of fast programming bits in flash EEPROM," Solid-State Electron., vol. 44, pp. 1887-1897, 2000.
22. F. Nkanash and M. Hatalies, "Effect of flash EEPROM floating gate morphology on electrical behavior of fast programming bits," IEEE Trans. Electron Devices, vol. 46, pp. 1355-1362, July 1999.
23. M. Wada, S. Mimura, H. Nihira, and H. Iuzuke, "Limiting factors for programming EPROM of reduced dimensions," in IEDM Tech. Dig., 1980, pp. 38-41.
24. S. Shishiguchi, T. Okamoto, K. Arai, and N. Shiegematsu, "The reduction of grain size in LPCVD poly-Si by in situ oxygen and phosphorus doping," J. Cryst. Growth, pp. 698-693, 1996.
25. S. Shimizu, T. Kuroi, A. Furukawa, Y. Nishida, Y. Nishida, Y. Inoue, M. Inuishi, and T. Nishimura, "Gale electrode engineering by control of grain growth for high performance and high reliable 0.18 um dual gate CMOS," in 1997 Symp. VLSI Technology, 1997, pp. 107-108.
26. T. Luoh, Y. C. Yang, B. Han, J. L. Su, H. H. Shih, K. C. Chen, C. C. Huseh, H.Henry Chung, S.Sam Pan, and C. Y. Lu, Floating gate engineering by single wafer processes for high reliable flash memory devices, to be published.
27. S. C. Wood and K. C. Saraswat, "Factors affecting the economic performance of cluster-based fabs'," in Proc. 3rd Int. Symp. VLSI Sci. Tech., Washington, DC, May 9, 1991, pp. 551-565.
28. P. Castrucci, J. Griffin, and M. Williams, "Design of single wafer future logic fabs," in 1994 IEEE/SEMI Adv, Semiconduct. Manufact. Conf., Cambridge, MA, 1994, pp. 1-3.