Novel nm-grain poly-Si gate structure for reduction of cell to cell write/erase tunnel current deviation in high speed quarter micron FLASH memories

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1997, Pages 115-116

  Yugami, Jiro ^a   Mine, Toshiyuki ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTERFACES (MATERIALS); SEMICONDUCTING FILMS; SEMICONDUCTOR STORAGE; SILICON ON INSULATOR TECHNOLOGY;

CELL TO CELL WRITE/ERASE TUNNEL CURRENT; LOCAL FIELD ENHANCEMENT; POLYSILICON GATE STRUCTURE; QUARTER MICRON FLASH MEMORIES;

SEMICONDUCTOR DEVICE STRUCTURES;

EID: 0030688144     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)