A novel method for worst-case interconnect delay estimation

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 50, Issue 6, 2003, Pages 778-781

  Chen, Bin ^a   Yang, Huazhong ^a   Luo, Rong ^a   Wang, Hui ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

Moment matching; Peak noise; Worst case delay

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; CROSSTALK; DELAY CIRCUITS; ESTIMATION; INTEGRATED CIRCUITS; NUMERICAL METHODS; SIGNAL PROCESSING; VLSI CIRCUITS;

WORST-CASE DELAYS;

ELECTRIC CONNECTORS;

EID: 0037480968     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2003.812619     Document Type: Article

References (19)

1. Semiconductor Industry Association, "National technology roadmap for semiconductors," Semiconductor Industry Association, San José, CA, 1999.
2. L. Nagel, "SPICE2, A computer program to simulate semiconductor circuits," Univ. California, Berkeley, CA, TR ERL-M520, May 1975.
3. W. C. Elmore, "The transient response of damped linear network with particular regard to wideband amplifiers," Appl. Phys., vol. 19, pp. 55-63, 1948.
4. R. Gupta, B. Tutuianu, and L. T. Pileggi, "The Elmore delay as a bound for RC trees with generalized input signal's," IEEE Trans. Computer-Aided Design, vol. 16, pp. 95-104, Jan. 1997.
5. A. B. Kahng and S. Muddu, "Two-pole analysis of interconnection trees," in Proc. IEEE Multi-Chip Module Conf., Santa Cruz, CA, Feb. 1995, pp. 105-110.
6. B. Tutuianu, F. Dartu, and L. Pileggi, "Explicit RC-circuit delay approximation based on the first three moments of the impulse response," in Proc. IEEE/ACM Design Automation Conf., June 1996, pp. 611-616.
7. C. J. Alpert and C. V. Kashyap, "RC delay metrics for performance optimization," IEEE Trans, Computer-Aided Design, vol. 20, pp. 571-582, May 2001.
8. H. Kawaguchi and T. Sakurai, "Delay and noise formulas for capacitively coupled distributed RC lines," in Proc. Asia-Pacific Design Automation Conf., 1998, pp. 25-43.
9. T. Sakurai, "Closed form expression for interconnection delay, coupling and crosstalk in VLSI's," IEEE Trans. Electron Devices, vol. 40, pp. 118-124, Jan. 1993.
10. A. Vittal and M. Marek-Sadowska, "Crosstalk reduction for VLSI," IEEE Trans. Computer-Aided Design, vol. 16, pp. 290-298, Mar. 1997.
11. Y. Eo, W. R. Eisenstadt, J. Y. Jeong, and O. K. Kwon, "A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design," IEEE Trans. Electron Devices, vol. 47, pp. 129-140, Jan. 2000.
12. A. Devgan, "Efficient coupled noise estimation for on-chip interconnects," in Proc. ICCAD'97, 1997, pp. 147-153.
13. A. Vittal, L. H. Chen, M. Sadowska, K. Wang, and S. Yang, "Crosstalk in VLSI interconnections," IEEE Trans. Computer-Aided Design, vol. 18, no. 12, pp. 1817-1824, Dec. 1999.
14. B. Chen, H. Z. Yang, and H. Wang, "Noise estimation for deep submicron integrated circuits," Sci. China, Ser. F, vol. 44, pp. 397-400, Oct. 2001.
15. A. B. Kahng, S. Muddu, and E. Sarto, "On switch factor based analysis of coupled RC interconnects," in Proc. Design Automation Conf., Los Angeles, CA, June 5-9, 2000, pp. 79-85.
16. G. Yee, R. Chandra, V. Ganesan, and C. Sechen, "Wire delay in the presence of crosstalk," in Proc. ACM/IEEE Int. Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Dec. 1997, pp. 170-175.
17. L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. Computer-Aided Design, vol. 9, pp. 352-366, Apr. 1990.
18. B. Chen, H. Z. Yang, R. Luo, and H. Wang, "Stable interconnect RC model via match the first two moments," in Proc. ICCCAS, Chengdu, China, June 29-July 1, 2002, pp. 1330-1333.
19. L. H. Chen and M. M. Sadowska, "Aggressor alignment for worst-case crosstalk noise," IEEE Trans. Computer-Aided Design, vol. 20, pp. 612-621, May 2001.