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Volumn 45, Issue 10, 1998, Pages 1107-1109

Evaluation of fast conversion techniques for binary-residue number systems

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BINARY CODES; NUMBER THEORY;

EID: 0032180134     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.728866     Document Type: Article
Times cited : (10)

References (14)
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    • Fast conversion between binary and residue numbers
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    • Electron. Lett.
    • Bi, G.1    Jones, E.V.2
  • 3
    • 0026400135 scopus 로고    scopus 로고
    • Novel RNS to binary converters
    • 91, Singapore, June 1991, pp. 1541-1544.
    • P. V. Ananda Mohan and D. V. PoornaiahNovel RNS to binary converters," in Proc. IEEE ISCAS'91, Singapore, June 1991, pp. 1541-1544.
    • Proc. IEEE ISCAS'
    • Ananda Mohan, P.V.1    Poornaiah, D.V.2
  • 4
    • 0028591373 scopus 로고    scopus 로고
    • Novel design for binary to RNS converters
    • 94, London, pp. 357-360.
    • P. V. Ananda MohanNovel design for binary to RNS converters," in Proc. IEEE ISCAS'94, London, pp. 357-360.
    • Proc. IEEE ISCAS'
    • Ananda Mohan, P.V.1
  • 5
    • 0026173991 scopus 로고    scopus 로고
    • Design of residue generators and multioperand modulo adders using carry-save adders
    • France, 1991, pp. 100-107.
    • S. J. PiestrakDesign of residue generators and multioperand modulo adders using carry-save adders," in Proc. 10th Symp. Computer Arithmetic, France, 1991, pp. 100-107.
    • Proc. 10th Symp. Computer Arithmetic
    • Piestrak, S.J.1
  • 6
    • 0026929779 scopus 로고    scopus 로고
    • Design of a residue arithmetic multiplier
    • vol. 139, pp. 581-585, 1992.
    • H. M. Razavi and J. BatteliniDesign of a residue arithmetic multiplier," Proc. Inst. Elect. Eng., G, vol. 139, pp. 581-585, 1992.
    • Proc. Inst. Elect. Eng., G
    • Razavi, H.M.1    Battelini, J.2
  • 9
    • 0024104425 scopus 로고    scopus 로고
    • A new efficient memoryless residue to binary converter
    • vol. CAS-35, pp. 1441-1444, Nov. 1988.
    • S. Andraros and H. AhmadA new efficient memoryless residue to binary converter," IEEE Trans. Circuits Syst., vol. CAS-35, pp. 1441-1444, Nov. 1988.
    • IEEE Trans. Circuits Syst.
    • Andraros, S.1    Ahmad, H.2
  • 10
    • 0029388575 scopus 로고    scopus 로고
    • A high speed realization of a residue to binary number system converter
    • vol. 42, pp. 661-663, 1995.
    • S. J. PiestrakA high speed realization of a residue to binary number system converter," IEEE Trans. Circuits Syst., vol. 42, pp. 661-663, 1995.
    • IEEE Trans. Circuits Syst.
    • Piestrak, S.J.1
  • 13
  • 14
    • 0020102009 scopus 로고    scopus 로고
    • A regular layout for parallel adders
    • vol. C-31, pp. 260-264, 1982.
    • R. P. Brent and H. T. KungA regular layout for parallel adders," IEEE Trans. Computers, vol. C-31, pp. 260-264, 1982.
    • IEEE Trans. Computers
    • Brent, R.P.1    Kung, H.T.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.