-
1
-
-
0021691117
-
A VLSI a algorithm for direct and reverse conversion from weighted binary number system to residue number
-
Dec.
-
G. Alia and Martinelli, "A VLSI a algorithm for direct and reverse conversion from weighted binary number system to residue number system" IEEE Trans. Circuits Systs., vol. CAS-31, pp. 1033-1039, Dec. 1984.
-
(1984)
System" IEEE Trans. Circuits Systs., Vol. CAS-31
, pp. 1033-1039
-
-
Alia, G.1
Martinelli2
-
2
-
-
0024070952
-
An efficient residue to binary converter design
-
Sept.
-
K. M. Ibrahim and S. Saloum, "An efficient residue to binary converter design," IEEE Trans. Circuits Syst., vol. 35, pp. 1156-1158, Sept. 1988.
-
(1988)
IEEE Trans. Circuits Syst.
, vol.35
, pp. 1156-1158
-
-
Ibrahim, K.M.1
Saloum, S.2
-
3
-
-
0024070868
-
Residue to binary conversion for RNS arithmetic using only modular look-up tables
-
Sept.
-
A. Shenoy and R. Kumaresan, " Residue to binary conversion for RNS arithmetic using only modular look-up tables," IEEE Trans. Circuits Syst., vol. 35, pp. 1158-1162, Sept. 1988.
-
(1988)
IEEE Trans. Circuits Syst.
, vol.35
, pp. 1158-1162
-
-
Shenoy, A.1
Kumaresan, R.2
-
4
-
-
0024104042
-
Efficient VLSI networks for converting an integer from binary system to residue number system and vice versa
-
Sept.
-
R. M. Capocelli and R. Giancarlo, "Efficient VLSI networks for converting an integer from binary system to residue number system and vice versa," IEEE Trans. Circuits Syst., vol. 35, pp. 1425-1431, Sept. 1988.
-
(1988)
IEEE Trans. Circuits Syst.
, vol.35
, pp. 1425-1431
-
-
Capocelli, R.M.1
Giancarlo, R.2
-
5
-
-
0024104425
-
A new efficient memoryless residue to binary converter
-
Sept.
-
S. Andraos and H. Ahmed, "A new efficient memoryless residue to binary converter," IEEE Trans. Circuits Syst., vol. 35, pp. 1441-1444, Sept. 1988.
-
(1988)
IEEE Trans. Circuits Syst.
, vol.35
, pp. 1441-1444
-
-
Andraos, S.1
Ahmed, H.2
-
6
-
-
0025446889
-
A universal input and output RNS converter
-
June
-
S. Meehan, S. O'Neil, and J. Vaccaro, "A universal input and output RNS converter," IEEE Trans. Circuits Syst., vol. 37, pp. 799-803, June 1990.
-
(1990)
IEEE Trans. Circuits Syst.
, vol.37
, pp. 799-803
-
-
Meehan, S.1
O'Neil, S.2
Vaccaro, J.3
-
7
-
-
0026852363
-
Fast and flexible architectures for RNS arithmetic decoding
-
Apr.
-
K. Elleithy and M. Bayoumi, "Fast and flexible architectures for RNS arithmetic decoding," IEEE Trans. Circuits Syst. II, vol. 39, pp. 226-234, Apr. 1992.
-
(1992)
IEEE Trans. Circuits Syst. II
, vol.39
, pp. 226-234
-
-
Elleithy, K.1
Bayoumi, M.2
-
8
-
-
0019654237
-
An efficient residue-to-decimal converter
-
Dec.
-
F. Taylor and A. Ramnarayanan, "An efficient residue-to-decimal converter," IEEE Trans. Circuits Syst., vol. 28, pp. 1164-1169, Dec. 1981.
-
(1981)
IEEE Trans. Circuits Syst.
, vol.28
, pp. 1164-1169
-
-
Taylor, F.1
Ramnarayanan, A.2
-
9
-
-
0021428663
-
Residue arithmetic: A tutorial with examples
-
May
-
F. Taylor, "Residue arithmetic: A tutorial with examples," IEEE Computer, pp. 50-62, May 1984.
-
(1984)
IEEE Computer
, pp. 50-62
-
-
Taylor, F.1
-
10
-
-
0019317268
-
Practical realization of mod p
-
June
-
A. Ramnarayanan, "Practical realization of mod p, p prime multiplier," Electron. Lett., vol. 16, pp. 466-467, June 1980.
-
(1980)
P Prime Multiplier," Electron. Lett.
, vol.16
, pp. 466-467
-
-
Ramnarayanan, A.1
-
11
-
-
0026896902
-
An RNS to binary converter in 2ra + 1, 2ra, 2ra -1 moduli set
-
A. B. Premkumar, "An RNS to binary converter in 2ra + 1, 2ra, 2ra -1 moduli set," IEEE Trans. Circuits Syst., vol. 39, pp. 480-482, July 1992.
-
(1992)
IEEE Trans. Circuits Syst.
, vol.39
, pp. 480-482
-
-
Premkumar, A.B.1
-
12
-
-
0027590244
-
Division techniques by integers of the form 2" ±1
-
F. Petry and P. Srinivasan, "Division techniques by integers of the form 2" ±1," Int. J. Electron., vol. 75, no. 5, pp. 659-670, 1993.
-
(1993)
Int. J. Electron.
, vol.75
, Issue.5
, pp. 659-670
-
-
Petry, F.1
Srinivasan, P.2
-
13
-
-
0028549334
-
Constant division algorithms
-
P. Srinivasan and F. Petry, "Constant division algorithms," in IEE Proc.-Comput. Digital Tech., 1994, vol. 141, no. 6, pp. 334-340.
-
IEE Proc.-Comput. Digital Tech., 1994
, vol.141
, Issue.6
, pp. 334-340
-
-
Srinivasan, P.1
Petry, F.2
-
14
-
-
0041478384
-
Decimal floating-point arithmetic in binary representation
-
E. Kaucher et al. Eds. Frankfurt, Germany: J. C. Balzer AG, 1991.
-
G. Bohlender, "Decimal floating-point arithmetic in binary representation," in Computer Arithmetic, Scientific Computation and Mathematical, E. Kaucher et al. Eds. Frankfurt, Germany: J. C. Balzer AG, 1991. pp. 13-27.
-
Computer Arithmetic, Scientific Computation and Mathematical
, pp. 13-27
-
-
Bohlender, G.1
-
15
-
-
0028338108
-
Design and analysis of nonbinary radix floating point representations
-
P. Johnstone and F. Petry, "Design and analysis of nonbinary radix floating point representations," Comput. Elect. Eng., vol. 20, no. 1, pp. 39-50, 1994.
-
(1994)
Comput. Elect. Eng.
, vol.20
, Issue.1
, pp. 39-50
-
-
Johnstone, P.1
Petry, F.2
-
16
-
-
33747805391
-
Rational number approximation in higher radix floating point systems
-
"Rational number approximation in higher radix floating point systems," Computers and Math. Applicat., vol. 25, no. 5, pp. 103-108, 1993.
-
(1993)
Computers and Math. Applicat.
, vol.25
, Issue.5
, pp. 103-108
-
-
|