Electro-thermal simulation for the prediction of chip operation within the package

Annual IEEE Semiconductor Thermal Measurement and Management Symposium

Volumn , Issue , 2003, Pages 168-175

  Rencz, M ^a   Szekely V ^b   Poppe, A ^a   Torki, K ^c   Courtois, B ^c  

^a MicReD Ltd   (Hungary)

^b BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS   (Hungary)

^c TIMA LABORATORY   (France)

Author keywords

Electro thermal simulation; Logi thermal simulation; Thermal modeling; Thermal simulation

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; LINEAR INTEGRATED CIRCUITS; TEMPERATURE; VLSI CIRCUITS; ANALOG CIRCUITS; CHIP SCALE PACKAGES; CIRCUIT SIMULATION; DIGITAL CIRCUITS; ELECTRONICS PACKAGING; INTEGRATED CIRCUITS; THERMAL VARIABLES MEASUREMENT; TIMING CIRCUITS;

ANALOG CIRCUITS; ELECTRO THERMAL SIMULATION; LOGI THERMAL SIMULATION;

INTEGRATED CIRCUIT LAYOUT; THERMAL CONDUCTIVITY;

ELECTRONIC PACKAGING THERMAL MANAGEMENTS; INTEGRATED CIRCUIT MODELING; INTEGRATED CIRCUIT PACKAGING; PREDICTIVE MODELS; TIMING;

EID: 0037272235     PISSN: 10652221     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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