A semi-synchronous circuit design method by clock tree modification

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E85-A, Issue 12, 2002, Pages 2596-2602

  Ishijima, Seiichiro ^a   Utsumi, Tetsuaki ^a,b   Oto, Tomohiro ^a   Takahashi, Atsushi ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b TOSHIBA CORPORATION   (Japan)

Author keywords

Clock tree; MIPS processor; Semi synchronous circuit

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; LOGIC DESIGN; PIPELINE PROCESSING SYSTEMS; SHIFT REGISTERS; VLSI CIRCUITS;

CLOCK TREE MODIFICATION; COMPLETE SYNCHRONOUS CIRCUIT; DEEP SUBMICRON CIRCUITS; LOGIC SYNTHESIS; SEMI-SYNCHRONOUS CIRCUIT;

INTEGRATED CIRCUIT LAYOUT;

EID: 0037004749     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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