A 200 MHz, 600 μw CMOS PLL for mobile communication ASICs

Proceedings - 12th Annual IEEE International ASIC/SOC Conference

Volumn , Issue , 1999, Pages 366-369

  Tourette, Bruno ^a  

^a NXP SEMICONDUCTORS   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ECONOMIC AND SOCIAL EFFECTS; INTEGRATED CIRCUIT DESIGN; PHASE LOCKED LOOPS;

CURRENT SOURCES; DESIGN TRADEOFF; LOW POWER; MAXIMUM OUTPUT; MOBILE COMMUNICATIONS;

MOBILE TELECOMMUNICATION SYSTEMS;

EID: 0013448577     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.1999.806536     Document Type: Conference Paper

References (1)

1. E. Nielson, US Patent 5614868, march 25, 1997