Power analysis of gated pipeline registers

Proceedings - 12th Annual IEEE International ASIC/SOC Conference

Volumn , Issue , 1999, Pages 281-285

  Ye, Wu ^a   Irwin, Mary Jane ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; PIPELINES; PROGRAMMABLE LOGIC CONTROLLERS;

ARCHITECTURAL LEVELS; CLOCK GATING; CONTROL SIGNAL; PIPELINE REGISTERS; POWER ANALYSIS; POWER OPTIMIZATION; SYSTEM ON CHIPS (SOC); SYSTEM RELIABILITY;

SYSTEM-ON-CHIP;

EID: 0002870677     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.1999.806520     Document Type: Conference Paper

References (10)

1. D. Burger, T. Austin, "The SimpleScalar Tool Set, Version 2. 0", Technical Report 1342, Computer Sciences Department, University of Wisconsin, Madison, Juno 1997.
2. Star-Hspica User's Manual Version 06. J, META-SOFTWARE, INC., February 1996.
3. U. Gloze, P. Blinzor, E. Cochlovius, M. Schafers, and K. Wachsmann, "VLSI Chip Design with The Hardware Description Language VERILOG: An Introduction Based on A Large RISC Processor Design", Springer-Verlag Berlin Heidelberg New York, 1996.
4. T. Lang, E. Musol, and J. Cortadella, "Individual Flip-Flops with Gated Clocks for Low Power Datapaths", IEEE Transactions on Circuits and System-II: Analog and Digital Signal Processing, Vol. 44. No. 6, June 1997.
5. H. Mehta, R. M Owens, M. J. Irwin, "Energy Characterization Based on Clustering", Proceedings of the 33rd Design Automation Conference, pp. 702, June 1996.
6. T. H. Meng, B, M. Gordon, E, K. Tsern, and A. C. Hung, "Portable Video-on-Demand in Wireless Communication", Proc. IEEE, Vol. 83, pp. 659, April 1995.
7. J. Montanaro, R. T. Witek, K. Anne, A. J. Black, and et al., "A 160-MHZ, 32-b, 0. 5-W CMOS RISC Microprocessor", IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, pp. 1703, Novembers 1996.
8. M. Ohnishi, A. Yamada, H. Noda, and T, Kambc, "A Method of Redundant Clocking Detection and Power Reduction at RT Level Design", Proc. of ISLPED'97, pp. 131, August 1997.
9. D. A. Patterson and J. L. Hennessy, Computer Organization & Design The Hardware/Software Interface, 2nd Edition, Morgan Kaufmann Publishers, Inc., San Francisco, California, 1998
10. V. Stojanovic, V. G. Oklobdxija, and R. Bajwa, "A Unified Approach in the Analysis of Latches and Flip-Flops for Low-Power Systems", Proc. of ISlPED'98, pp. 227, August 1998.