Tuning of loop cache architectures to programs in embedded system design

Proceedings of the International Symposium on System Synthesis

Volumn , Issue , 2002, Pages 8-13

  Cotterell, Susan ^a   Vahid, Frank ^b  

^a University of California Riverside   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Architecture tuning; Cores; Customized architectures; Embedded systems; Filter cache; Instruction fetching; Loop cache; Low energy; Low power; Memory hierarchy; Synthesis; Tuning

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; EMBEDDED SYSTEMS; SYSTEMS ANALYSIS;

CUSTOMIZED ARCHITECTURE; FILTER CACHE; INSTRUCTION FETCHING; LOOP CACHE; MEMORY HIERARCHY;

PROGRAM PROCESSORS;

EID: 0036953664     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/581199.581204     Document Type: Conference Paper

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