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Volumn , Issue , 2002, Pages 219-224

Low-power data memory communication for application-specific embedded processors

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; POWER CONTROL; TELECOMMUNICATION LINKS;

EID: 0036949102     PISSN: 10801820     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/581244.581248     Document Type: Conference Paper
Times cited : (7)

References (13)
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    • Petrov, P.1    Orailoglu, A.2
  • 2
    • 0032628047 scopus 로고    scopus 로고
    • A coding framework for low-power address and data busses
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    • S. Ramprasad and N. R. Shanbhag, "A coding framework for low-power address and data busses", IEEE TVLSI, vol. 7, pp. 212-221, June 1999.
    • (1999) IEEE TVLSI , vol.7 , pp. 212-221
    • Ramprasad, S.1    Shanbhag, N.R.2
  • 3
    • 0030684367 scopus 로고    scopus 로고
    • Analytical energy dissipation models for low-power caches
    • August
    • M. B. Kamble and K. Ghose, "Analytical energy dissipation models for low-power caches", in ISLPED, pp. 143-148, August 1997.
    • (1997) ISLPED , pp. 143-148
    • Kamble, M.B.1    Ghose, K.2
  • 4
    • 0033358971 scopus 로고    scopus 로고
    • Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation
    • August
    • K. Ghose and M. B. Kamble, "Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation", in ISLPED, pp. 70-75, August 1999.
    • (1999) ISLPED , pp. 70-75
    • Ghose, K.1    Kamble, M.B.2
  • 5
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    • Using dynamic cache management techniques to reduce energy in a high-performance processor
    • August
    • N. Bellas, I. Hajj and C. Polychronopoulos, "Using dynamic cache management techniques to reduce energy in a high-performance processor", in ISLPED, pp. 64-69, August 1999.
    • (1999) ISLPED , pp. 64-69
    • Bellas, N.1    Hajj, I.2    Polychronopoulos, C.3
  • 6
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    • Bus-invert coding for low-power I/O
    • March
    • M. R. Stan and W. P. Burleson, "Bus-invert coding for low-power I/O", IEEE TVLSI, vol. 3, pp. 49-58, March 1995.
    • (1995) IEEE TVLSI , vol.3 , pp. 49-58
    • Stan, M.R.1    Burleson, W.P.2
  • 7
    • 0030644909 scopus 로고    scopus 로고
    • Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems
    • March
    • L. Benini et al., "Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems", in 7th GLSVLSI, pp. 77-82, March 1997.
    • (1997) 7th GLSVLSI , pp. 77-82
    • Benini, L.1
  • 8
    • 0034869584 scopus 로고    scopus 로고
    • Irredundant address bus encoding for low-power
    • August
    • Y. Aghaghiri, F. Fallah and M. Pedram, "Irredundant address bus encoding for low-power", in ISLPED, pp. 182-187, August 2001.
    • (2001) ISLPED , pp. 182-187
    • Aghaghiri, Y.1    Fallah, F.2    Pedram, M.3
  • 9
    • 0034869199 scopus 로고    scopus 로고
    • Low power address encoding using self-organizing lists
    • August
    • M. Mamidipaka, D. Hirschberg and N. Dutt, "Low power address encoding using self-organizing lists", in ISLPED, pp. 188-193, August 2001.
    • (2001) ISLPED , pp. 188-193
    • Mamidipaka, M.1    Hirschberg, D.2    Dutt, N.3
  • 10
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    • The cache performance and optimizations of blocked algorithms
    • April
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  • 11
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    • A data locality optimizing algorithm
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  • 13
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    • C. Lee, M. Potkonjak and W. H. Mangione-Smith, "MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems", in 30th MICRO, pp. 330-335, December 1997.
    • (1997) 30th MICRO , pp. 330-335
    • Lee, C.1    Potkonjak, M.2    Mangione-Smith, W.H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.