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Volumn 23, Issue 12, 2002, Pages 1267-1274

Structure design considerations of a sub-50 nm self-aligned double-gate MOSFET

Author keywords

Double gate MOSFET; SCD; Sidewall effect; Structure design

Indexed keywords

FABRICATION; SILICON; STRUCTURAL DESIGN;

EID: 0036923062     PISSN: 02534177     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (1)

References (10)
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    • Lee J H, Taraschi G, Wei A, et al. Super self-aligned double-gate (SSDG) MOSFETs utilizing oxidation rate difference and selective epitaxy. Proc IEDM, 1999: 71.
    • (1999) Proc. IEDM , pp. 71
    • Lee, J.H.1    Taraschi, G.2    Wei, A.3
  • 5
    • 0030271147 scopus 로고    scopus 로고
    • A comparative study of advanced MOSFET concepts
    • Wann C H, Noda K, Tanaka T, et al. A comparative study of advanced MOSFET concepts. IEEE Trans Electron Devices, 1996, 43 (10): 1742
    • (1996) IEEE Trans. Electron Devices , vol.43 , Issue.10 , pp. 1742
    • Wann, C.H.1    Noda, K.2    Tanaka, T.3
  • 6
    • 0023421993 scopus 로고
    • Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance
    • Balestra F, Cristoloveabu S. Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performance. IEEE Electron Device Lett, 1987 (8): 410
    • (1987) IEEE Electron. Device Lett. , Issue.8 , pp. 410
    • Balestra, F.1    Cristoloveabu, S.2
  • 8
    • 0032284102 scopus 로고    scopus 로고
    • Device design consideration for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25nm channel length generation
    • Wong H S, Frank D J, Solomn P M. Device design consideration for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25nm channel length generation. Proc IEDM, 1998: 407
    • (1998) Proc. IEDM , pp. 407
    • Wong, H.S.1    Frank, D.J.2    Solomn, P.M.3
  • 9
    • 0032070926 scopus 로고    scopus 로고
    • Semiconductor thickness effects in the double-gate SOI MOSFET
    • Maklisoml B, Janik T, Walczak J. Semiconductor thickness effects in the double-gate SOI MOSFET. IEEE Trans Electron Devices, 1998, 45 (5): 1127
    • (1998) IEEE Trans. Electron Devices , vol.45 , Issue.5 , pp. 1127
    • Maklisoml, B.1    Janik, T.2    Walczak, J.3
  • 10
    • 0003552056 scopus 로고    scopus 로고
    • The national technology roadmap for semiconductors (NTRS)
    • Semiconductor Industry Association (USA), San Jose, CA 95129
    • Semiconductor Industry Association (USA). The national technology roadmap for semiconductors (NTRS). San Jose, CA 95129, 2001.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.