Performance and Reliability Comparison between Asymmetric and Symmetric LDD Devices and Logic Gates

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 3, 1999, Pages 367-371

  Chen, Jone F ^a,b,c,d,e   Tao, Jiang ^b,d   Fang, Peng ^b   Hu, Chenming ^a,d,f  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b ADVANCED MICRO DEVICES   (United States)

^c NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e MOTOROLA INC   (United States)

^f MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Hot carriers; Integrated circuit reliability; Semiconductor device reliability

Indexed keywords

HOT CARRIERS; INTEGRATED CIRCUIT TESTING; LOGIC GATES; RELIABILITY; SEMICONDUCTOR DOPING;

LIGHTLY DOPED DRAIN (LDD) DEVICES;

MOSFET DEVICES;

EID: 0033098648     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.748188     Document Type: Article

References (14)

1. S. Ogura, P. J. Tsang, W. W. Walker, D. L. Critchlow, and J. F. Shepard, "Design and characteristics of the lightly doped drain-source (LDD) insulated gate field effect transistor," IEEE Trans. Electron Devices, vol. ED-27, no. 8, p. 1359, 1980.
2. - impurity profiles," in IEDM Tech. Dig., 1985, p. 246.
3. C.-Y. Wei, J. M. Pimbley, and Y. Nissan-Cohen, "Buried and graded/buried LDD structure for improved hot-electron reliability," IEEE Electron Device Lett., vol. EDL-7, no. 6, p. 380, 1986.
4. G. Krieger, R. Sikora, P. Cuevas, and M. Misheloff, "Moderately doped NMOS (M-LDD) - Hot electron and current drive optimization," IEEE Trans. Electron Devices, vol. 38, no. 1, p. 121, 1991.
5. F. Matsuoka, K. Kasai, H. Oyamatsu, M. Kinugawa, and K. Maeguchi, "Drain structure optimization for highly reliable deep submicron n-channel MOSFET," IEEE Trans. Electron Devices, vol. 41, no. 3, p. 420, 1991.
6. T. N. Buti, S. Ogura, N. Rovedo, K. Tobimatsu, and C. F. Codella, "Asymmetric halo source GOLD drain (HS-GOLD) deep sub-half micron n-MOSFET design for reliability and performance," in IEDM Tech. Dig., 1989, p. 617.
7. T. Horiuchi, T. Homma, Y. Murao, and K. Okumura, "An asymmetric sidewall process for high performance LDD MOSFET's," IEEE Trans. Electron Devices, vol. 41, no. 2, p. 186, 1994.
8. R. H. Tu, E. Rosenbaum, W. Y. Chan, C. C. Li, E. Minami, K. Quader, P. K. Ko, and C. Hu, "Berkeley reliability tools-BERT," IEEE Trans. Computer-Aided Design, vol. 12, no. 10, p. 1524, 1993.
9. "BTABERT User's Manual," BTA Technology, Inc., Santa Clara, CA, 1996.
10. C. Dai, S. V. Walstra, and S.-W. Lee, "The effect of intrinsic capacitance degradation on circuit performance," in Symp. VLSI Technology Tech. Dig., 1996, p. 196.
11. W. Weber, M. Brox, T. Kunemund, H. M. Muhlhoff, and D. Schmitt-Landsiedel, "Dynamic degradation in MOSFET's - Part II: Application in the circuit environment," IEEE Trans. Electron Devices, vol. 38, no. 8, p. 1859, 1991.
12. P. M. Lee, "New insights in optimizing CMOS inverter circuits with respect to hot-carrier degradation," IEICE Trans. Electron., p. 194, 1994.
13. K. N. Quader, E. R. Minami, W.-J. Huang, P. K. Ko, and C. Hu, "Hot-carrier-reliability design rules for translating device degradation to CMOS digital circuit degradation," IEEE J. Solid-State Circuits, vol. 29, no. 3, p. 681, 1994.
14. K. R. Mistry, R. Hokinson, B. Gieseke, T. F. Fox, R. P. Preston, and B. S. Doyle, "Voltage overshoots and n-MOSFET hot carrier robustness in VLSI circuits," in Proc. IEEE Int. Reliability Physics Symp., 1994, p. 65.