Memory accesses reordering for interconnect power reduction in sum-of-products computations

IEEE Transactions on Signal Processing

Volumn 50, Issue 11, 2002, Pages 2889-2899

  Masselos, Konstantinos ^a,b,c   Theoharis, Spyros ^d   Merakos, Panagiotis ^c,e   Stouraitis, Thanos ^a,c   Goutis, Costas E ^a,c  

^a IEEE   (Greece)

^b Intracom Holdings SA   (Greece)

^c UNIVERSITY OF PATRAS   (Greece)

^d ALMA Technologies SA   (Greece)

^e Athena SEMI SA   (Greece)

Author keywords

High level synthesis; Interconnect; Low power; Memory; Sum of products

Indexed keywords

DATA MEMORIES; HIGH LEVEL SYNTHESIS; POWER CONSUMPTION;

ALGORITHMS; DATA STORAGE EQUIPMENT; MATHEMATICAL MODELS; TRAVELING SALESMAN PROBLEM;

DIGITAL SIGNAL PROCESSING;

EID: 0036842604     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSP.2002.804060     Document Type: Article

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