Activity Measures for Fast Relative Power Estimation in Numerical Transformation for Low Power DSP Synthesis

Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

Volumn 18, Issue 1, 1998, Pages 25-38

  Nguyen, Huy T ^a,c,d,e   Chatterjee, Abhijit ^a,f,g,h,i,j   Roy, Rabindra K ^b,h,i,k,l  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b INTEL CORPORATION   (United States)

^c UNIVERSITY OF DELAWARE   (United States)

^d GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^e GEORGIA TECH RESEARCH INSTITUTE   (United States)

^f INDIAN INSTITUTE OF TECHNOLOGY KANPUR   (India)

^g UNIVERSITY OF ILLINOIS AT CHICAGO   (United States)

^h UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

ⁱ GE GLOBAL RESEARCH   (United States)

^j IEEE

^k INDIAN INSTITUTE OF TECHNOLOGY   (India)

^l NEC LABORATORIES AMERICA   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CALCULATIONS; GRAPH THEORY; NUMERICAL METHODS; SWITCHING;

ACTIVITY TRANSFORMATION MODELS; NUMBER-SPLITTING;

DIGITAL SIGNAL PROCESSING;

EID: 0031655209     PISSN: 13875485     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (20)

1. R. Lyon, "Two's complement pipeline multipliers," IEEE Communication, COMM-12, April 1976, pp. 418-425.
2. K. Hwang, Computer Arithmetic, Principles, Architecture, and Design, Wiley, New York, 1979.
3. F. Najm, "Transition density, a stochastic measure of activity in digital circuits," 28th ACM/IEEE Design Automation Conference, p. 644, 1991.
4. A. Ghosh, S. Devadas, K. Keutzer, and J. White, "Estimation of average switching activity in combinational and sequential circuits," Proceedings of the 29th Design Automation Conference, pp. 253-259, 1992.
5. C. Tsui, M. Pedram, and A. Despain, "Exact and approximation methods for calculating signal and transition probabilities in FSMs," 31st ACM/IEEE Design Automation Conference, pp. 18-23, 1994.
6. T.-L. Chou, K. Roy, and S. Prasad, "Estimation of circuit activity considering signal correlations and simultaneous switching," IEEE Intl. Conf. on Computer-Aided-Design, pp. 300-303, 1994.
7. Y. Lin, C. Liu, and Z. Shen, "A cell-based power estimation in CMOS combinational circuits," Proceedings of the IEEE Intern. Conf. on Computer-Aided Design, pp. 304-309, 1994.
8. J. Monteiro and S. Dvadas, "A methodology for efficient estimation of switching activity in sequential logic circuits," 31st ACM/IEEE Design Automation Conference, pp. 12-17, 1994.
9. K. Roy and S. Prasad, "Circuit activity based logic synthesis for low power reliable operations," IEEE Trans. on VLSI Systems, pp. 503-513, Dec. 1993.
10. S. Powell and P. Chau, "A model for estimating power dissipation in a class of DSP VLSI chips," IEEE Trans. Circuits Systems, Vol. 36, No. 6, pp. 644-650, June 1995.
11. A. Raghunathan and N. Jha, "Behavioral synthesis for low power," ICCD, pp. 318-322, 1994.
12. P. Landman and J. Rabaey, "Power estimation for high level synthesis," EDAC/EURO-ASIC 93, pp. 361-366, 1993.
13. A. Chandrakasan, M. Potkonjak, J. Rabaey, and R. Bordersen, "HYPER-LP: A system for power minimization using architectural transformations," International Conference on Computer Aided Design, pp. 300-303, 1992.
14. A. Chatterjee and R. Roy, "Synthesis of low-power linear DSP circuits using activity metrics," 7th International Conference on VLSI Design, pp. 265-270, Jan. 1994.
15. A. Chatterjee and R. Roy, "An architectural transformation program for optimization of digital system by multilevel decomposition," 30th ACM/IEEE Design Automation Conference, p. 343, 1993.
16. H.T. Nguyen and A. Chatterjee, "Number-splitting with shift-and-add decomposition for power and hardware optimization in linear systems synthesis," submitted to IEEE Trans. on VLSI Systems, 1997.
17. A. Oppenheim and R. Schafer, Discrete-Time Signal Processing, Prentice-Hall Publisher, Englewood-Cliffs, NJ, 1989.
18. M. Potkonjak and J. Rabaey, "Exploring the algorithmic design space using high level synthesis," VLSI Design Methodologies for Digital Signal Processing Architectures, Kluwer Academic Publishers, pp. 129-167, 1994.
19. M. Pedram, "Power minimization in IC design: Principles and applications," ACM Transactions on Design Automation of Electronic Systems, Vol. 1, No. 1, pp. 3-56, Jan. 1996.
20. T.L. Chou and K. Roy, "Statistical estimation of sequential circuit activity," Intl. Conf. Computer Aided Design (ICCAD-95), pp. 34-37, Nov. 1995.