Low-power realization of FIR filters on programmable DSP's

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 6, Issue 4, 1998, Pages 546-553

  Mehendale, Mahesh ^a,b   Sherlekar, Sunil D ^a,c   Venkatesh, G ^c  

^a IEEE   (India)

^b TEXAS INSTRUMENTS   (India)

^c Silicon Automation Systems   (India)

Author keywords

Finite impulse response (FIR) filters; Low power design; Programmable digital signal processing (DSP)

Indexed keywords

ALGORITHMS; DIGITAL SIGNAL PROCESSING; ENERGY DISSIPATION;

PROGRAMMABLE DIGITAL SIGNAL PROCESSORS;

FIR FILTERS;

EID: 0032300756     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.736126     Document Type: Article

References (17)

1. E. A. Lee, "Programmable DSP architectures: Part I," IEEE ASSP Mag., Oct. 1988, pp. 4-19.
2. TMS320C2x/C5x User's Guides, Texas Instruments, 1993.
3. A. P. Chandrakasan and R. W. Brodersen, "Minimizing power consumption in digital CMOS circuits," Proc. IEEE, Apr. 1995, pp. 498-523.
4. C.-L. Su, C.-Y. Tsui, and A. M. Despain, "Saving power in the control path of embedded processors," IEEE Design Test Comput., pp. 24-30, Winter 1994.
5. J. Bradley, "Calculation of TMS320C5x power dissipation application report," Texas Instruments, 1993.
6. G.-K. Ma and F. J. Taylor, "Multiplier policies for digital signal processing," IEEE ASSP Mag., Jan. 1990, pp. 6-19.
7. F. Najm, "Transition density: A new measure of activity in digital circuits," IEEE Trans. Computer-Aided Design, pp. 310-323, Feb. 1993.
8. M. T.-C. Lee, V. Tiwari, S. Malik, and M. Fujita, "Power analysis and minimization techniques for embedded DSP software," IEEE Trans. VLSI Syst., pp. 123-135, Mar. 1997.
9. K. K. Parhi, "Algorithms and architectures for high-speed and low-power digital signal processing," in Proc. 4th Int. Conf. Advances in Commun. Contr., Rhodes, Greece, June 1993.
10. M. Mehendale, S. D. Sherlekar, and G. Venkatesh, "Extensions to programmable DSP architectures for reduced power dissipation," in Proc. 11th Int. Conf. VLSI Design, Jan. 1998.
11. L. Benini, G. D. Micheli, E. Macii, D. Sciuto, and C. Silvano, "Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems," in Proc. GLS-VLSI'97, 7th Great Lakes Symp. VLSI, Mar. 1997.
12. M. R. Stan and W. P. Burleson, "Bus invert coding for low power I/O," IEEE Trans. VLSI Syst., Mar. 1995.
13. TMS320C54x User's Guide, Texas Instruments, 1995.
14. D. Kodek and K. Steiglitz, "Comparison of optimal and local search methods for designing finite wordlength FIR digital filters," IEEE Trans. Circuits Syst., Jan. 1981, pp. 28-32.
15. H. Samueli, "An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients," IEEE Trans. Circuits Syst., July 1989, pp. 1044-1047.
16. Z. J. Mou and P. Duhamel, "Short-length FIR filters and their use in fast nonrecursive filtering," IEEE Trans. Signal Processing, June 1991, pp. 1322-1323.
17. E. L. Lawler, J. K. Lenstra, A. H. G. Rinnooy Kan, and D. B. Shmoys, Eds., The Travelling Salesman Problem. New York: Wiley, 1985.