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Volumn 1918, Issue , 2000, Pages 243-254

Data-reuse and parallel embedded architectures for low-power, real-time multimedia applications

Author keywords

[No Author keywords available]

Indexed keywords

MEMORY ARCHITECTURE; MOTION ESTIMATION; PARALLEL ARCHITECTURES; VIDEO SIGNAL PROCESSING;

EID: 84944181132     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45373-3_26     Document Type: Conference Paper
Times cited : (22)

References (12)
  • 3
    • 0032689802 scopus 로고    scopus 로고
    • Strategy for Power Efficient Design of Parallel Systems
    • June
    • K. Masselos, F. Catthoor, H. De Man, and C.E. Goutis, and “Strategy for Power Efficient Design of Parallel Systems”, in IEEE Trans. on VLSI, vol. 7, No. 2, June 1999, pp. 258-265.
    • (1999) In IEEE Trans on VLSI , vol.7 , Issue.2 , pp. 258-265
    • Masselos, K.1    Catthoor, F.2    De Man, H.3    Goutis, C.E.4
  • 4
    • 0005363452 scopus 로고    scopus 로고
    • Data-reuse exploration for lowpower realization of multimedia applications on embedded cores
    • October
    • N. D. Zervas, K. Masselos, and C.E. Goutis,”Data-reuse exploration for lowpower realization of multimedia applications on embedded cores”, in Proc Of PATMOS’99, October 1999, pp. 71-80.
    • (1999) Proc of PATMOS’99 , pp. 71-80
    • Zervas, N.D.1    Masselos, K.2    Goutis, C.E.3
  • 5
    • 0032710725 scopus 로고    scopus 로고
    • Hierarchical Algorithm Partitioning at System Level for an Improved Utilization of Memory Structures
    • January
    • U. Eckhardt and R. Merker,”Hierarchical Algorithm Partitioning at System Level for an Improved Utilization of Memory Structures”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 18, No. 1, January 1999, pp. 14-23.
    • (1999) IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol.18 , Issue.1 , pp. 14-23
    • Eckhardt, U.1    Merker, R.2
  • 6
    • 0032303141 scopus 로고    scopus 로고
    • Formalized Methodology for Data Reuse Exploration for Low-Power Hierarchical Memory Mappings
    • Dec
    • S. Wuytack, J.-P. Diguet, F. Catthoor, D. Moolenaar, and H. De Man “Formalized Methodology for Data Reuse Exploration for Low-Power Hierarchical Memory Mappings”, in IEEE Trans. on VLSI Systems, Vol. 6, No. 4, Dec. 1998, pp. 529-537.
    • (1998) IEEE Trans on VLSI Systems , vol.6 , Issue.4 , pp. 529-537
    • Wuytack, S.1    Diguet, J.-P.2    Catthoor, F.3    Moolenaar, D.4    De Man, H.5
  • 9
  • 12
    • 84944252129 scopus 로고    scopus 로고
    • ARM software development toolkit, v2.11, Copyright, 7, Advanced RISC Machines
    • ARM software development toolkit, v2.11, Copyright 1996-7, Advanced RISC Machines.
    • (1996)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.