Fault simulation based test generation for combinational circuits using dynamically selected subcircuits

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1999, Pages 412-417

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC FAULT CURRENTS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

DYNAMIC CIRCUIT PARTITIONING METHOD; DYNAMICALLY SELECTED SUBCIRCUITS; FAULT SIMULATION-BASED METHOD;

VLSI CIRCUITS;

EID: 0033299274     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Article

References (16)