High-performance logic and high-gain analog CMOS transistors formed by a shadow-mask technique with a single implant step

IEEE Transactions on Electron Devices

Volumn 49, Issue 9, 2002, Pages 1623-1627

  Hook, Terence B ^a,b   Brown, Jeffery S ^b   Breitwisch, Matthew ^b   Hoyniak, Dennis ^b   Mann, Randy ^a,b  

^a IEEE   (United States)

^b IBM MICROELECTRONICS   (United States)

Author keywords

Analog integrated circuits; CMOSFETS

Indexed keywords

ANALOG INTEGRATED CIRCUITS; DRAIN CONDUCTANCE; DRAIN CURRENT; DRAIN VOLTAGE; HALO IMPLANT; PHOTORESIST MASK; SHADOW MASK TECHNIQUE; SHORT CHANNEL EFFECTS;

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC CONDUCTANCE; ELECTRIC FIELD EFFECTS; GAIN MEASUREMENT; GATES (TRANSISTOR); MASKS; MOSFET DEVICES; PERFORMANCE; PHOTORESISTS; SEMICONDUCTOR DEVICE STRUCTURES; THRESHOLD VOLTAGE;

CMOS INTEGRATED CIRCUITS;

EID: 0036712445     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2002.802623     Document Type: Article

References (6)

1. 50-nm gate length CMOS transistor with super halo: Design, process, and reliability
2. Impact of pocket implant and channel interface modeling on the reverse short channel effect
3. Implications of pocket optimization on analog performance in deep submicron CMOS
4. Process outlook for analog and RF applications
5. Modeling of pocket implanted MOSFETs for anomalous analog behavior
6. 'System on a chip' technology for 0.18-μm digital, mixed signal and eDRAM applications