A 0.18μm 256Mb DDR-SDRAM with low-cost post-mold-tuning method for DLL replica

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 402-403

  Kuge, S ^a   Kato, T ^a   Furutani, K ^a   Kikuda, S ^a   Mitsui, K ^a   Hamamoto, T ^a   Setogawa, J ^a   Hamade, K ^a   Komiya, Y ^a   Kawasaki, S ^a   Kono, T ^a   Amano, T ^a   Kubo, T ^a   Haraguchi, M ^a   Kawaguchi, Z ^a   Nakaoka, Y ^a   Akiyama, M ^a   Konishi, Y ^a   Ozaki, H ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIT ERROR RATE; CAPACITORS; MICROPROCESSOR CHIPS; ROM; SHIFT REGISTERS; STATIC RANDOM ACCESS STORAGE;

VOLTAGE DOWN CONVERTER (VDC);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0034429686     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)