A 66-400 MHz, adaptive-lock-mode DLL circuit with duty-cycle error correction

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2001, Pages 37-38

  Okuda, Y ^a   Horiguchi, M ^a   Nakagome, Y ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BUFFER CIRCUITS; DIFFERENTIAL AMPLIFIERS; DYNAMIC RANDOM ACCESS STORAGE; ERROR CORRECTION;

DELAY-LOCKED LOOP (DLL) CIRCUITS;

DELAY CIRCUITS;

EID: 0034784819     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. A dynamic voltage scaled microprocessor system
2. A 256-Mb double-data-rate SDRAM with 10mW analog DLL circuit